AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 21

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
state is in COUNT, the state machine switches to the BEAT4 state to terminate the cycle with TA and
AACK.
For any cycles which cannot be handled by the memory controller, DOERR_L will be asserted. This is
caused either by address-only cycles or specialized data transfer instructions (lwarx, etc.); for such cycles,
the state machine will assert TEA and AACK. The behavior of PowerPC processors does not specify what
happens when TEA is asserted during address-only cycles; however, since this minimal system environment
disallows such cycles, the resulting behavior is allowable (either the cycles are silently ignored and
processing resumes, or the processor takes an exception).
In all these cases, AACK is not asserted until the last (or only) TA is asserted, releasing the address tenure
as well as the data tenure. The re-assertion delay inherent before TS can be asserted guarantees a one-clock
cycle recovery time on the data bus.
The VHDL code for this module is:
------------------------------------------------------------------------------------------------
-- D:\USR\GMILLI~1\MC\CYCLER\CYCLER.VHD
-- VHDL code created by Visual Software Solution's StateCAD Version 3.2
-- Thu Sep 24 16:16:39 1998
-- This VHDL code (for use with Workview Office) was generated using:
-- one-hot state assignment with boolean code format.
-- Minimization is enabled, implied else is enabled,
-- and outputs are manually optimized.
--LIBRARY LAT_VHD;
--USE LAT_VHD.VHD_PKG.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY synth;
USE synth.vhdlsynth.all;
ENTITY SHELL_CYCLER IS
END;
ARCHITECTURE BEHAVIOR OF SHELL_CYCLER IS
BEGIN
PORT (CLK,CLAIM_L,CTIME0,CTIME1,CTIME2,CTIME3,DOERR_L,RST_L,SCS_L,TBST_L,
SIGNAL TIMER0,TIMER1,TIMER2,TIMER3: std_logic;
-- State variables for machine sreg
SIGNAL BEAT1, next_BEAT1, BEAT2, next_BEAT2, BEAT3, next_BEAT3, BEAT4,
SIGNAL next_TIMER0,next_TIMER1,next_TIMER2,next_TIMER3 : std_logic;
SIGNAL TIMER : std_logic_vector (3 DOWNTO 0);
ATTRIBUTE PERMEABILITY OF BEHAVIOR: ARCHITECTURE IS TRUE;
PROCESS (CLK, RST_L, next_BEAT1, next_BEAT2, next_BEAT3, next_BEAT4,
BEGIN
WE_L: IN std_logic;
AACK_L,ADSC_L,BAA_L,TA_L,TEA_L : OUT std_logic);
next_BEAT4, BURST, next_BURST, CLOCK, next_CLOCK, COUNT, next_COUNT, DESEL,
next_DESEL, ERROR, next_ERROR, IDLE, next_IDLE, SINGLE, next_SINGLE :
std_logic;
next_BURST, next_CLOCK, next_COUNT, next_DESEL, next_ERROR, next_IDLE,
next_SINGLE, next_TIMER3, next_TIMER2, next_TIMER1, next_TIMER0)
IF ( RST_L='0' ) THEN
ELSIF CLK='1' AND CLK'event THEN
BEAT1 <= '0';
BEAT2 <= '0';
BEAT3 <= '0';
BEAT4 <= '0';
BURST <= '0';
CLOCK <= '0';
COUNT <= '0';
DESEL <= '0';
ERROR <= '0';
IDLE <= '1';
SINGLE <= '0';
TIMER3 <= '0';
TIMER2 <= '0';
TIMER1 <= '0';
TIMER0 <= '0';
BEAT1 <= next_BEAT1;
Freescale Semiconductor, Inc.
For More Information On This Product,
Minimal PowerPC System Design
Go to: www.freescale.com
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