AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 9

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
Note that 16-bit devices have been used. This helps reduce the number of components, at a cost of restricting
writes to 16, 32 or 64 bits in size. If 8-bit writes are required, then either 8 8-bit devices must be used, or
devices which have multiple byte enables.
A further restriction on ßash memory is that reading is slow (from 60 to 200 ns), and writing is even slower
(as much as 15 ms). The memory controller delays the assertion of TA for a Þxed number of cycles on any
access to match the read time; this handles the read access properly and gives sufÞcient time for the ßash
device to begin the program operation (the data does not need to be held throughout a write cycle).
Software must insure that a proper amount of time has elapsed after a write before another read or write
occurs. This can be done with a simple timing loop, using I/O to check the RDY/BSY signals, or the use of
ßash devices which can be queried by reading special addresses.
3.3 I/O Controls
Most simple I/O devices such as real-time clocks, serial ports, and other unique interfaces have fairly simple
I/O controlsÑa chip select, an output enable, and a write control. The I/O controller can then be modeled
very closely on the ßash ROM controller; both have simple controls and both are relatively slow.
One difference between ßash ROM and I/O is that most I/O devices are 8 or perhaps 16 bits, not 64, so I/O
devices must be attached to particular byte lanes. The I/O controller responds to any size write, so data may
be placed on any byte lane (software is responsible for positioning and retrieving the data properly). A fairly
easy modiÞcation to the controller allows different I/O times for each address decoded, allowing fast and
slow I/O devices to be mixed.
Note that the write strobes/direction control are the same byte write enables that have been described before.
This reuse will allow a reduction of the size and complexity of the controller, but it also means that the
software must generate the correct address when performing writes to I/O devices greater than 8 bits wide.
For example, in Figure 6, a 16-bit I/O device is attached to D(0Ð15) and uses BWE1, so to access the
controller, software must issue 16- or 32-bit writes aligned with D0. The controller will assert BWE1 (all
others are ignored).
The I/O controller supports both Motorola and PC control signals. In addition, these devices attach to the
3.3-V PowerPC data bus, so they must not drive over 3.3V. An easy solution to this is to add a 3.3-V buffer
between the high-speed memory path and the I/O devices, which has a side beneÞt of allowing faster
memory operation due to reduced capacitive loading.
BWE0
XCS0
BWE1
XCS1
XOE
Freescale Semiconductor, Inc.
For More Information On This Product,
Minimal PowerPC System Design
Figure 6. I/O Connections
Go to: www.freescale.com
RD
WE
CS
OE
R/W
CS
PC
I/O Device
Motorola
I/O Device
Remember:
3.3V Devices
ONLY!
D(0Ð15)
D(0Ð7)
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