AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 18

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

The code for this module is:
18
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-- CHIPSEL.VHD
--
-- CHIPSEL() is the portion of the MC which decodes addresses
--
--
--
-- Copyright 1998, by Motorola Inc.
-- All rights reserved.
--
-- Author:
-- Revision: 0.2
-- Date:
-- Notes:
--
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
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-- CHIPSEL
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ENTITY CHIPSEL is
end; --PORT DEFINITION AND ENTITY
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ARCHITECTURE BEHAVIOR OF CHIPSEL is
BEGIN
-- Assert chip select if cycle is claimed and corresponding address is presented.
scs_L <= Õ0Õ
xcs_L(0) <= Õ0Õ WHEN (a = "01" and claim_L = Õ0Õ)
xcs_L(1) <= Õ0Õ WHEN (a = "10" and claim_L = Õ0Õ)
fcs_L <= Õ0Õ
-- Assert corresponding output enables (OE_L) if the cycle is claimed and is not
-- a write cycle.
soe_L <= Õ0Õ
xoe_L <= Õ0Õ
foe_L <= Õ0Õ
PORT( a
-- Provide corresponding timer value. Note that SRAM is not timer controlled, so any
-- value may be used. All of these values should be changed if the bus frequency is
-- changed. If the clock rate is increased, the system may fail. If lowered, clock
-- cycles will be wasted.
-- Note: there is a three clock overhead in the setup and termination of timed cycles
-- (one on entry, one during AACK/TA*, and one exiting when the timer is zero). Therefore,
-- timing constants are offset by (-3).
SET_TIMER : PROCESS( fcs_L, xcs_L(0) )
BEGIN
IF (fcs_L = Õ0Õ) THEN
and provides corresponding chip select outputs, along with a clock
timer value which determines the rate of memory accesses.
);
claim_L
we_L
scs_L, soe_L
fcs_L, foe_L
xcs_L
xoe_L
ctime
ctime <= "0011";
Gary Milliorn
6/10/98
All logic is active low when appended with a "_L".
Passed speedwave check 6/16/98.
WHEN (a = "00" and claim_L = Õ0Õ)
ELSE Õ1Õ;
ELSE Õ1Õ;
ELSE Õ1Õ;
WHEN (a = "11" and claim_L = Õ0Õ)
ELSE Õ1Õ;
WHEN (
ELSE Õ1Õ;
WHEN ( (a = "01" and claim_L = Õ0Õ and we_L = Õ1Õ)
ELSE Õ1Õ;
WHEN (
ELSE Õ1Õ;
Freescale Semiconductor, Inc.
For More Information On This Product,
or (a = "10" and claim_L = Õ0Õ and we_L = Õ1Õ))
Minimal PowerPC System Design
a = "00" and claim_L = Õ0Õ and we_L = Õ1Õ)
a = "11" and claim_L = Õ0Õ and we_L = Õ1Õ)
: in
: in
: in
: buffer std_logic;
: buffer std_logic;
: buffer std_logic_vector( 0 to 1 );
: buffer std_logic;
: buffer std_logic_vector( 3 downto 0 )-- 4-bit time value.
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std_logic_vector( 0 to 1 );
std_logic;
std_logic;
-- Flash:
80 ns @ 15ns clocks (66 MHz) = 6 -3 => 3 clocks.
-- stable 60X bus address
-- asserted for active cycles.
-- asserted for write cycles.
-- SRAM chip-selects & enables.
-- Flash chip-selects & enables.
-- I/O chip selects.
-- I/O output enable.
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