AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 29

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AN1769

Manufacturer Part Number
AN1769
Description
Designing a Minimal PowerPC System
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
MOTOROLA
Figure 15 shows pipelined burst SRAMs that need ADSC asserted to start, then TA asserted for a burst of
four beats for the data. After the Þrst beat, BAA is asserted to increment the address to the next location. At
the end of each transfer, ADSC is strobed to deselect the SRAM.
CLK
A_HIGH0
A_HIGH1
A_LOW29
A_LOW30
A_LOW31
TT0
TT1
TT2
TT3
TT4
TSIZ0
TSIZ1
TSIZ2
TBST_L
TS_L
AACK_L
TA_L
TEA_L
ADSC_L
BAA_L
SCS_L
SOE_L
BWE_L0
BWE_L1
BWE_L2
BWE_L3
BWE_L4
BWE_L5
BWE_L6
BWE_L7
RST_L
HRESET_L
!RESET
COPHRST_L
MRESET
T(CLK)
Figure 15. Pipelined Burst SRAMÑBurst Read/Write
Freescale Semiconductor, Inc.
For More Information On This Product,
1u
Minimal PowerPC System Design
Go to: www.freescale.com
2u
Time (Seconds)
3u
4u
5u
29

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