AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 5

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
Part 3 Memory System Design
The one fairly complicated portion of a minimal system is the interface to the processor data bus. Unlike
CISC processors, RISC processors do not typically perform data (re)alignment, so the data from each
external device must be placed on the proper data lane. To attempt to use an 8-bit memory device to supply
instructions or data to a 64-bit data bus, 8-bidirectional latching transceivers must be used to move the byte
to the correct byte lane on the 64-bit bus, as shown in Figure 2.
Because the processor expects from one to eight bytes on each (non-burst) transfer, the memory controller
must generate from one to eight memory cycles to the 8-bit memory by generating the address(es), latching
the resulting data, and then presenting it to the processor with the TA signal. This process must be reversed
when writing to memory. This can take signiÞcant amounts of logic, and is the approach taken by the
MPC106 ROM interface, for example.
For this minimal system, we will instead take the approach that all memory is 64-bits wide. By using 32-bit
pipelined-burst SRAM for the main memory and 16-bit Flash EPROM for start-up code, only 6 components
will be needed, the controlling logic will be simple and inexpensive, and as a bonus the SRAM will allow
very fast memory access speeds. The use of SRAM for main memory has become more attractive as speed
and size increases and price falls. Currently SRAM devices at 66 MHz are commodity components due to
their use as L2 caches in PCs; even 100-MHz parts are not terribly expensive. The minimal system block
diagram is shown in Figure 3.
MPC60x
Freescale Semiconductor, Inc.
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Minimal PowerPC System Design
Figure 2. Byte Lane Redirection
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