AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 38

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

This approach does have several limitations for the MCP interrupt; in particular, the HID0[EMCP] bit and
MSR[ME] enable bits must be properly set, and the interrupt remains edge-sensitive unless additional
external hardware is used.
For systems needing a more traditional interrupt controller, many FPGA vendors offer IP cores which
implement PC-style Ò8259Ó programmable interrupt controllers (PIC). There are sufÞcient resources in
most FPGAs to include it with the memory controller by adding additional I/O controls, an 8-bit data bus,
and INT output, and 1Ð-n interrupt inputs. Such an interrupt controller can include other advanced features
such as edge-sensitive to level-sensitive conversion, and interrupt prioritizing and masking.
Excimer uses a very simple interrupt merging system, though provisions are in place to add programmable
I/O to do interrupt masking.
The VHDL code for the Excimer interrupt controller is:
38
------------------------------------------------------------------------------------------------
-- INT.VHD
--
-- INT() is a small interrupt controller for the Excimer project which
-- fits in some available gates of the Memory Controller (MC).
--
-- Copyright 1998, by Motorola Inc.
-- All rights reserved.
--
-- Author:
-- Revision: 0.1
-- Date:
-- Notes:
--
--
-------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--==============================================================================================
-- INT
------------------------------------------------------------------------------------------------
ENTITY INT is
end; --PORT DEFINITION AND ENTITY
------------------------------------------------------------------------------------------------
ARCHITECTURE BEHAVIOR OF INT is
BEGIN
END BEHAVIOR;
------------------------------------------------------------------------------------------------
PORT( irq
int_L <= '0' WHEN ( (irq(0) = '1') or (irq(1) = '1')
);
int_L
Gary Milliorn
6/30/98
All logic is active low when appended with a "_L".
Passed speedwave check 6/30/98.
ELSE '1';
Freescale Semiconductor, Inc.
or (irq(2) = '0') or (irq(3) = '0'))
Level Sensitive
Edge Sensitive
For More Information On This Product,
: in
: buffer std_logic
Minimal PowerPC System Design
Interrupts
Interrupts
Figure 27. Interrupt Reuse
Go to: www.freescale.com
std_logic_vector( 0 to 3 );
INT0
INT1
INT2
INT
SMI
MCP
PowerPC
-- interupt inputs (variable polarity)
-- interrupt output.
-- active high interrupts
-- active low interrupts.
MOTOROLA