AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 26

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

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BEGIN
END COMPONENT;
COMPONENT START
PORT( tt_take
END COMPONENT;
COMPONENT TTDEC
PORT( tt
END COMPONENT;
SIGNAL tt_take
SIGNAL tt_we_L
SIGNAL we_L
SIGNAL claim_L
SIGNAL doerr_L
SIGNAL ctime
SIGNAL aack_internal_L
TTDEC_1
START_1
CHIPSEL_1
BYTEDEC_1 : BYTEDEC PORT MAP (
CYCLER_1 : CYCLER PORT MAP (
-- Copy internal aack to external aack, since VHDL is fussy about connecting OUT's to BUFFER's.
aack_L <= '0' WHEN (aack_internal_L = '0')
-- The databus port is not currently used; add logic to use it to maintain its existance,
-- otherwise errors will be generated for unused ports.
probe1 <= '0' WHEN (d = "11111111")
------------------------------------------------------------------------------------------------
-- Sideband modules that are not part of the memory controller but are needed for the Excimer
-- project include the interrupt controller, reset drivers and LED monitors.
-- Extremely simple interrupt controller -- the databus is wired and ready to accept a more
-- complicated version, if desired.
);
);
ts_L
aack_L
clk
rst_L
claim_L
doerr_L
we_L
tt_take
tt_we_L
monitor
tt_we_L
: TTDEC PORT MAP (
: START PORT MAP (
);
);
: CHIPSEL PORT MAP (
);
);
);
tt => tt, tt_take => tt_take, tt_we_L => tt_we_L, monitor => monitor1
tt_take => tt_take, tt_we_L => tt_we_L, ts_L => ts_L, aack_L => aack_internal_L,
clk => clk, rst_L => rst_L,
claim_L => claim_L, doerr_L => doerr_L, we_L => we_L
a => a_high, claim_L => claim_L, we_L => we_L, scs_L => scs_L, soe_L => soe_L,
fcs_L => fcs_L, foe_L => foe_L, xcs_L => xcs_L, xoe_L => xoe_L,
ctime => ctime
a => a_low, tsiz => tsiz, tbst_L => tbst_L,
claim_L => claim_L, we_L => we_L,
bwe_L => bwe_L
CTIME => ctime, CLK => clk, CLAIM_L => claim_L,
DOERR_L => doerr_L, RST_L => rst_L, SCS_L => scs_L, TBST_L => tbst_L,
ELSE '1';
ELSE '1';
AACK_L => aack_internal_L, ADSC_L => adsc_L, BAA_L => baa_L,
TA_L => ta_L, TEA_L => tea_L
Freescale Semiconductor, Inc.
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Minimal PowerPC System Design
: in
: in
: in
: in
: buffer std_logic;
: buffer std_logic;
: buffer std_logic
: buffer std_logic;
: buffer std_logic;
: buffer std_logic
: in
: in
: in
: std_logic;
: std_logic;
: std_logic;
: std_logic;
: std_logic;
: std_logic_vector( 3 downto 0 );
: std_logic;
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std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic_vector( 0 to 4 );
-- transfer start strobe.
-- asserted on transfer complete.
-- bus clock.
-- system reset.
-- asserted when cycle is claimed.
-- asserted when cycle not claimed.
-- byte lane write selects.
-- asserted when TT matches types.
-- asserted when cycle is write.
-- unneeded, ViewSynthesis bug.
-- asserted if good TT selection.
-- asserted if good TT is write.
-- current transfer type.
-- asserted for TT matches.
-- asserted for write cycles.
-- asserted for cycles to process.
-- asserted for cycles to TEA*
-- selected cycle time.
-- internal copy.
-- asserted for TT match writes.
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