AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 2

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/SPS/PowerPC/.
Part 1 Introduction
To keep the design simple, only the most basic features necessary to run a debugger program are included.
These features are as follows:
While this application note is general in focus, it will also occasionally diverge in order to describe the
implementation details of an actual board, known as ÒExcimer,Ó which implements the basic techniques
described in this application note. The details of Excimer provide a base upon which you can build a design,
with the general sections describing ways to support customization.
1.1 Design Philosophy
The PowerPC high-performance family (MPC60x and MPC7xx) bus interface may at Þrst appear
intimidating due to the presence of split address/data bus tenuring, bus snooping, multiprocessing support,
cache coherency support, and other advanced features. Such features can be used to obtain additional
performance for high-performance systems, but for the purposes of a small, high-speed embedded controller
(particularly one with only one bus master), many of these complications can be avoided.
Since the processor does not contain an internal memory controller or I/O interface, that role has
traditionally fallen to the Motorola MPC106 memory/PCI/cache controller. For a small board such as
outlined here, the MPC106 is much more than is minimally needed. Indeed, complexity can sometimes
reduce performance. Cache coherency instructions use valuable bus cycles, and allowing access by external
masters (such as cache) requires delaying memory cycles in case the external device claims the cycle.
Instead, for this design, a programmable ASIC is used to provide the necessary controls for a block of RAM,
ROM and access to I/O. The controller is not programmable by software but is instead pre-conÞgured in
hardware, and memory access cycles are tuned to provide only the necessary signals.
With these restrictions and goals, the typical block diagram may resemble that shown in Figure 1.
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Part 8, ÒCOPÓ
Part 9, ÒPhysical LayoutÓ
Part 10, ÒConclusionÓ
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A PowerPC processor (this includes the MPC603e, MPC603ev, MPC604, MPE603e, MPE603ev,
MPE604, MPC740 and MPC750)
Flash ROM storage (start-up code)
Read/write memory (downloaded code, program variables)
Serial I/O channel (communication)
Memory and I/O controller
Power, clocks and reset
Freescale Semiconductor, Inc.
For More Information On This Product,
Minimal PowerPC System Design
Go to: www.freescale.com
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MOTOROLA