AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 19

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
The chipsel() module is asynchronous because it relies on the synchronous signal, claim_L, and relies on
the stability of the address bus (a) and write select (we_L) signals. These latter two signals are guaranteed
to be stable until TA is asserted because the cycler() module also delays the assertion of AACK until the last
TA.
The chip-select module may be easily adapted to different device speeds, and for different I/O maps (within
PowerPC architecture limitations). It may also be modiÞed to provide access to internal register Þles or to
increase the number of chip selects, within limitations of the FPGA chosen.
3.5.4 Cycler State Machine
The cycler() state machine module controls the remainder of any transaction claimed by the memory
controller. For optimal performance, one of four ßows are selected. The ßows are as follows:
The Þrst two optimize speed for the SRAM accesses, which are typically the majority of code and data
accesses; the latter are handled in a more programmed method. Fortunately, the streamlined nature of burst
transfers keeps the cycler() module from becoming too complicated.
Cycler() Þnishes any non-error transaction by asserting AACK and TA (one to four times, based upon the
type of cycle). When AACK is generated, the cycle has been completed and a new one can begin at the next
clock cycle. Due to the pipelining nature of the SRAM, it actually takes 5 beats to do a read cycle, but one
of those clock cycles has already been provided before cycler() can leave the IDLE state by the synchronous
start() detector. Figure 12 shows the end-cycle module.
As the VHDL code for the cycler() is generated by a state-machine CAD program, the code is uncommented
and somewhat difÞcult to follow; refer instead to Figure 13 for details.
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END BEHAVIOR;
------------------------------------------------------------------------------------------------
SRAM single beat transfer
SRAM burst transfer
Programmed-length transfer (I/O and Flash)
Error transactions
END IF;
END PROCESS SET_TIMER;
ELSIF (xcs_L(0) = Õ0Õ) THEN
ELSE
ctime <= "1001";
ctime <= "0001";
CTIME(0Ð3)
DOERR_L
CLAIM_L
SCS_L
Freescale Semiconductor, Inc.
TBST
RST
CLK
For More Information On This Product,
Minimal PowerPC System Design
Figure 12. End-Cycle Module
Go to: www.freescale.com
4
-- Slow I/O: 180 ns @ 15ns clocks (66 MHz) = 12 -3 => 9 clocks.
-- Fast I/O: 60 ns @ 15ns clocks (66 MHz) = 4 -3 => 1 clocks.
cycler
TEA
AACK
BAA
TA
ADSC
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