AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 25

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------------------------
-- MC
------------------------------------------------------------------------------------------------
ENTITY MC is
end; --PORT DEFINITION AND ENTITY
------------------------------------------------------------------------------------------------
ARCHITECTURE BEHAVIOR OF MC is
COMPONENT BYTEDEC
PORT( a
END COMPONENT;
COMPONENT CHIPSEL
PORT( a
END COMPONENT;
COMPONENT INT
PORT( irq
END COMPONENT;
COMPONENT CYCLER
PORT( CTIME
PORT( clk, rst_L
);
);
);
a_high
a_low
ts_L
tt
tsiz
tbst_L
irq
altrst_L
cophrst_L
bwe_L
scs_L, soe_L
fcs_L, foe_L
xcs_L
xoe_L
ta_L, tea_L
aack_L
adsc_L
baa_L
int_L
hreset_L
mreset
fcsled, scsled
xcsled
d
probe1
monitor1
tsiz
tbst_L
claim_L
we_L
bwe_L
claim_L
we_L
scs_L, soe_L
fcs_L, foe_L
xcs_L
xoe_L
ctime
int_L
CLK,CLAIM_L,DOERR_L,
RST_L,SCS_L,TBST_L : IN std_logic;
AACK_L,ADSC_L,BAA_L,
TA_L,TEA_L
);
);
Freescale Semiconductor, Inc.
For More Information On This Product,
Minimal PowerPC System Design
: in
: in
: in
: in
: in
: in
: in
: in
: in
: buffer std_logic_vector( 0 to 7 );
: buffer std_logic_vector( 0 to 1 );
: buffer std_logic;
: out
: out
: out
: out
: buffer std_logic;
: buffer std_logic;
: buffer std_logic;
: buffer std_logic;
: buffer std_logic;
: in
: buffer std_logic;
: buffer std_logic
: in
: in
: in
: in
: buffer std_logic_vector( 0 to 7 )
: in
: in
: buffer std_logic_vector( 0 to 1 );
: buffer std_logic;
: buffer std_logic_vector( 3 downto 0 )-- 4-bit time value.
: buffer std_logic
: OUT std_logic
: in
: buffer std_logic;
: buffer std_logic;
: buffer std_logic;
: buffer std_logic;
: in
: in
: in
: IN std_logic_vector (3 DOWNTO 0);
Go to: www.freescale.com
std_logic_vector( 0 to 1 );
std_logic_vector( 29 to 31 ); -- lower 60X bus address
std_logic;
std_logic_vector( 0 to 4 );
std_logic_vector( 0 to 2 );
std_logic;
std_logic_vector( 0 to 3 );
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic_vector( 0 to 7 );
std_logic_vector( 0 to 2 );
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic_vector( 0 to 3 );
std_logic_vector( 29 to 31 ); -- stable 60X bus address
std_logic_vector( 0 to 1 );
-- SRAM chip-selects & enable.
-- Flash chip-selects & enable.
-- SRAM chip-selects & enable.
-- Flash chip-selects & enable.
-- upper 60X address
-- transfer start.
-- transfer type.
-- transfer size.
-- asserted if transfer is burst.
-- interrupt inputs.
-- alternate reset input.
-- COP port HRESET input.
-- byte lane write selects.
-- I/O chip selects.
-- I/O output enable.
-- normal and error acks.
-- address acks.
-- SRAM address latch.
-- SRAM burst address advance.
-- interrupt output.
-- CPU HRESET* output.
-- Misc active-high reset output.
-- LED output drivers.
-- "
-- data bus input.
-- internal monitors.
-- ViewSynthesis bug.
-- current transfer size.
-- asserted if transfer is burst.
-- asserted if transfer is claimed.
-- asserted if transfer is write.
-- byte lane write selects.
-- asserted for active cycles.
-- asserted for write cycles.
-- I/O chip selects.
-- I/O output enable.
-- interrupt output.
-- general controls.
-- interupt inputs (var. polarity)
-- stable 60X bus address
25