XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 18

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: Processor Block
Debug Interface
Debugging interfaces on the PPC405 core, consisting of the
JTAG and Trace ports, offer access to resources internal to
the core and assist in software development. The JTAG port
provides basic JTAG chip testing functionality as well as the
ability for external debug tools to gain control of the proces-
sor for debug purposes. The Trace port furnishes program-
mers with a mechanism for acquiring instruction execution
traces.
The JTAG port complies with IEEE Std 1149.1, which
defines a test access port (TAP) and boundary scan
architecture. Extensions to the JTAG interface provide
debuggers with processor control that includes stopping,
starting, and stepping the PPC405 core. These extensions
are compliant with the IEEE 1149.1 specifications for
vendor-specific extensions.
The Trace port provides instruction execution trace informa-
tion to an external trace tool. The PPC405 core is capable of
back trace and forward trace. Back trace is the tracing of
instructions prior to a debug event while forward trace is the
tracing of instructions after a debug event.
The processor JTAG port can be accessed independently
from the FPGA JTAG port, or the two can be programmati-
cally linked together and accessed via the FPGA’s dedi-
cated JTAG pins.
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CoreConnect™ Bus Architecture
The Processor Block is compatible with the CoreConnect™
bus architecture. Any CoreConnect compliant cores includ-
ing Xilinx soft IP can integrate with the Processor Block
through this high-performance bus architecture imple-
mented on FPGA fabric.
The CoreConnect architecture provides three buses for
interconnecting Processor Blocks, Xilinx soft IP, third party
IP, and custom logic, as shown in
•
•
•
High-performance peripherals connect to the high-band-
width, low-latency PLB. Slower peripheral cores connect to
the OPB, which reduces traffic on the PLB, resulting in
greater overall system performance.
For more information, refer to:
http://www-3.ibm.com/chips/techlib/techlib.nfs
/productfamilies/CoreConnect_Bus_Architecture/
Processor Local Bus (PLB)
On-Chip Peripheral Bus (OPB)
Device Control Register (DCR) bus
System
Core
Figure 6: CoreConnect Block Diagram
Processor Local Bus
Instruction
System
Core
Processor
Block
Data
System
Core
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Bridge
DCR Bus
Bus
DCR
Bus
Figure
CoreConnect Bus Architecture
Peripheral
On-Chip Peripheral Bus
Core
6:
Peripheral
DS083-2_02a_010202
Core
R