XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 90

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

DCM Timing Parameters
Miscellaneous Timing Parameters
Table 48: Miscellaneous Timing Parameters
Frequency Synthesis
Table 49: Frequency Synthesis
90
Notes:
1.
Time Required to Achieve LOCK
Fine Phase Shifting
Delay Lines
CLKFX_MULTIPLY
CLKFX_DIVIDE
Using DLL outputs
Using CLKFX outputs
Additional lock time with fine phase
shifting
Absolute shifting range
Tap delay resolution
“”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
Attribute
Description
(1)
Min
LOCK_DLL:
LOCK_FX_MIN
LOCK_FX_MAX
LOCK_DLL_FINE_SHIFT
FINE_SHIFT_RANGE
DCM_TAP_MIN
DCM_TAP_MAX
2
1
LOCK_DLL_60
LOCK_DLL_50_60
LOCK_DLL_40_50
LOCK_DLL_30_40
LOCK_DLL_24_30
Symbol
Max
32
32
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1-800-255-7778
> 60MHz
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
24 - 30 MHz
Constraints
F
CLKIN
–8
Speed Grade
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
–7
–6
Units
ms
ms
us
us
us
us
us
us
ns
ps
ps
R