XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 9

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

DS083-2 (v1.0) January 31, 2002
Virtex-II Pro Array Functional
Description
This module describes the following Virtex-II Pro functional
components, as shown in
•
•
Functional Description: Rocket I/O
Multi-Gigabit Transceiver (MGT)
This section summarizes the features of the Rocket I/O
multi-gigabit transceiver. For an in-depth discussion of the
Rocket I/O MGT, refer to the Rocket I/O User Guide.
Overview
The embedded Rocket I/O multi-gigabit transceiver core is
based on Mindspeed’s SkyRail™ technology. Up to sixteen
transceiver cores are available. The transceiver core is
designed to operate at any baud rate in the range of
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Figure 1: Virtex-II Pro Generic Architecture Overview
Embedded Rocket I/O™ Multi-Gigabit Transceivers
(MGTs)
Processor Blocks containing embedded IBM
PowerPC
integration circuitry.
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
®
405 RISC CPU (PPC405) cores and
SelectI/O™-Ultra
CLB
DCM
Figure
Configurable
Logic
CLB
CLB
Multi-Gigabit Transceiver
R
1:
Rocket I/O™
CLB
DS083-1_01_010802
®
0
0
www.xilinx.com
1-800-255-7778
0
Virtex-II Pro™ Platform FPGAs:
Functional Description
Advance Product Specification
•
For a detailed description of the PPC405 core programming
models and internal core operations, refer to the PowerPC
405 User Manual and the Processor Block Manual.
For detailed Rocket I/O digital and analog design consider-
ations, refer to the Rocket I/O User Guide.
All of the documents above, as well as a complete listing
and description of Xilinx-developed Intellectual Property
cores for Virtex-II Pro, are available on the Xilinx website at
www.xilinx.com/virtex2pro.
Virtex-II Pro Compared to Virtex-II Devices
Virtex-II Pro is built on the Virtex-II FPGA architecture. Most
FPGA features are identical to Virtex-II. The differences are
described below:
•
•
•
•
622 Mb/s to 3.125 Gb/s per channel. This includes specific
baud rates used by various standards as listed in
.
Table 1: Standards Supported by the Rocket I/O MGT
Fibre Channel
Gbit Ethernet
XAUI
FPGA fabric based on Virtex-II architecture.
Virtex-II Pro is the first FPGA family incorporating
embedded PPC405 cores and Rocket I/O MGTs.
V
3.3V as for Virtex-II devices. Advanced processing at
0.13 m has resulted in a smaller die, faster speed,
and lower power consumption.
The Virtex-II Pro family is neither bitstream-compatible
nor pin-compatible with the Virtex-II family. However,
Virtex-II designs can be compiled into Virtex-II Pro
devices.
All banks support 2.5V (and below) I/O standards.
3.3V I/O standards including PCI are supported in
certain banks only. (See
LVDS_33, LVDSEXT_33, LVDCI_DV2_33, and
AGP-2X are not supported.
Mode
CCAUX
, the auxiliary supply voltage, is 2.5V instead of
Channels
(Lanes)
1
1
4
Table 4
Baud Rate
(Gb/s)
3.125
1.06
2.12
1.25
I/O
in Module 4.) LVPECL,
Rate (REFCLK)
Internal Clock
156.25
(MHz)
62.5
106
53
Table
1.
9