XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 23

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Table 3: Supported Single-Ended I/O Standards
Table 4: Supported Differential Signal I/O Standards
All of the user IOBs have fixed-clamp diodes to V
ground. The IOBs are not compatible or compliant with 5V
I/O standards (not 5V tolerant).
Table 5
trolled Impedance. See
(DCI), page
Table 5: Supported DCI I/O Standards
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Notes:
1. V
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
LDT_25
LVDS_25
LVDSEXT_25
BLVDS_25
ULVDS_25
LVDCI_33
LVDCI_25
LVDCI_DV2_25
LVDCI_18
LVDCI_DV2_18
LVDCI_15
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
Standard
Standard
termination voltage or the voltage seen at the I/O pad.
Standard
CCO
I/O
I/O
I/O
lists supported I/O standards with Digitally Con-
of GTL or GTLP should not be lower than the
(1)
R
27.
Output
V
Output
2.5
2.5
2.5
2.5
2.5
V
CCO
2.5
3.3
3.3
2.5
CCO
Output
V
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
CCO
Digitally Controlled Impedance
Input
V
N/A
N/A
N/A
N/A
N/A
Input
V
CCO
N/A
N/A
N/A
N/A
CCO
Input
V
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
CCO
Input
V
N/A
N/A
N/A
N/A
N/A
Input
V
REF
1.25
1.25
1.5
1.5
Input
REF
V
0.75
0.75
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
1.0
0.9
0.9
REF
0.500 - 0.740
0.250 - 0.400
0.250 - 0.450
0.500 - 0.740
0.330 - 0.700
Termination
Termination
CCO
Output
Voltage
Board
V
(V
Series
Series
Series
Series
Series
Series
Series
Single
Single
Single
Single
1.25
1.25
1.5
1.5
Type
OD
Split
Split
TT
and to
www.xilinx.com
)
1-800-255-7778
Table 5: Supported DCI I/O Standards (Continued)
Logic Resources
IOB blocks include six storage elements, as shown in
Figure
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in
and 3-state data signals, each being alternately clocked out.
Virtex-II Pro™ Platform FPGAs: Functional Description
Notes:
1. LVDCI_XX is LVCMOS controlled impedance buffers,
2. These are SSTL compatible.
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
matching the reference resistors or half of the reference
resistors.
Standard
10.
I/O
OCK2
OCK2
OCK1
OCK1
Reg
Reg
Reg
Reg
Figure 10: Virtex-II Pro IOB Block
(2)
(2)
(2)
(2)
DDR mux
DDR mux
3-State
Output
Output
Figure
V
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
CCO
11. There are two input, output,
Input
V
IOB
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
CCO
Input
V
1.08
1.08
1.25
1.25
0.9
0.9
1.5
1.5
REF
ICK1
ICK2
Reg
Reg
Input
PAD
DS031_29_100900
Termination
Single
Single
Type
Split
Split
Split
Split
Split
Split
23