XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 32

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
Register/Latch
The storage elements in a Virtex-II Pro slice can be config-
ured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D input can be directly driven by
the X or Y output via the DX or DY input, or by the slice
inputs bypassing the function generators via the BX or BY
input. The clock enable signal (CE) is active High by default.
If left unconnected, the clock enable for that storage ele-
ment defaults to the active state.
In addition to clock (CK) and clock enable (CE) signals,
each slice has set and reset signals (SR and BY slice
inputs). SR forces the storage element into the state speci-
fied by the attribute SRHIGH or SRLOW. SRHIGH forces a
logic 1 when SR is asserted. SRLOW forces a logic 0. When
SR is used, an optional second input (BY) forces the stor-
age element into the opposite state via the REV pin. The
reset condition is predominant over the set condition. (See
Figure
The initial state after configuration or global initial state is
defined by a separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.
For each slice, set and reset can be set to be synchronous
or asynchronous. Virtex-II Pro devices also have the ability
to set INIT0 and INIT1 independent of SRHIGH and
SRLOW.
The control signals clock (CLK), clock enable (CE) and
set/reset (SR) are common to both storage elements in one
slice. All of the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
32
CLK
Figure 23: Register / Latch Configuration in a Slice
CE
SR
BY
BX
23.)
DX
DY
D
CE
CK
D
CE
CK
SR REV
SR REV
FFY
FFX
FF
LATCH
FF
LATCH
Q
Q
Attribute
Attribute
DS083-2_22_122001
Reset Type
INIT1
INIT0
SRHIGH
SRLOW
INIT1
INIT0
SRHIGH
SRLOW
SYNC
ASYNC
YQ
XQ
www.xilinx.com
1-800-255-7778
Table 10: Distributed SelectRAM Configurations
The set and reset functionality of a register or a latch can be
configured as follows:
•
•
•
•
•
•
•
The synchronous reset has precedence over a set, and an
asynchronous clear has precedence over a preset.
Distributed SelectRAM Memory
Each function generator (LUT) can implement a 16 x 1-bit
synchronous RAM resource called a distributed SelectRAM
element. The SelectRAM elements are configurable within
a CLB to implement the following:
•
•
•
•
•
•
•
Distributed SelectRAM memory modules are synchronous
(write) resources. The combinatorial read access time is
extremely fast, while the synchronous write simplifies
high-speed designs. A synchronous read can be imple-
mented with a storage element in the same slice. The dis-
tributed SelectRAM memory and the storage element share
the same clock input. A Write Enable (WE) input is active
High, and is driven by the SR input.
Table 10
by each distributed SelectRAM configuration.
Notes:
1. S = single-port configuration; D = dual-port configuration
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
Single-Port 16 x 8-bit RAM
Single-Port 32 x 4-bit RAM
Single-Port 64 x 2-bit RAM
Single-Port 128 x 1-bit RAM
Dual-Port 16 x 4-bit RAM
Dual-Port 32 x 2-bit RAM
Dual-Port 64 x 1-bit RAM
shows the number of LUTs (2 per slice) occupied
128 x 1S
16 x 1D
32 x 1D
64 x 1D
16 x 1S
32 x 1S
64 x 1S
RAM
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Number of LUTs
1
2
2
4
4
8
8
R