XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 49

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

•
Configuration
Virtex-II Pro devices are configured by loading application
specific configuration data into the internal configuration
memory. Configuration is carried out using a subset of the
device pins, some of which are dedicated, while others can
be re-used as general purpose inputs and outputs once
configuration is complete.
Depending on the system design, several configuration
modes are supported, selectable via mode pins. The mode
pins M2, M1 and M0 are dedicated pins. An additional pin,
HSWAP_EN is used in conjunction with the mode pins to
select whether user I/O pins have pull-ups during configura-
tion. By default, HSWAP_EN is tied High (internal pull-up)
which shuts off the pull-ups on the user I/O pins during con-
figuration. When HSWAP_EN is tied Low, user I/Os have
pull-ups during configuration. Other dedicated pins are
CCLK (the configuration clock pin), DONE, PROG_B, and
the boundary-scan pins: TDI, TDO, TMS, and TCK.
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or an input accepting
an externally generated clock. The configuration pins and
boundary scan pins are independent of the V
iliary power supply (V
See
A persist option is available which can be used to force the
configuration pins to retain their configuration function even
after device configuration is complete. If the persist option is
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Virtex-II Pro Switching Characteristics (Module
R
24 Horizontal Long Lines
24 Vertical Long Lines
120 Horizontal Hex Lines
120 Vertical Hex Lines
40 Horizontal Double Lines
40 Vertical Double Lines
16 Direct Connections
(total in all four directions)
8 Fast Connects
CCAUX
) of 2.5V is used for these pins.
Figure 52: Hierarchical Routing Resources
CCO
. The aux-
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3).
not selected then the configuration pins with the exception
of CCLK, PROG_B, and DONE can be used as user I/O in
normal operation. The persist option does not apply to the
boundary-scan related pins. The persist feature is valuable
in applications which employ partial reconfiguration or
reconfiguration on the fly.
Virtex-II Pro supports the following five configuration
modes:
•
•
•
•
•
Refer to
A detailed description of configuration modes is provided in
the Virtex-II Pro User Guide.
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The CCLK pin on the FPGA is an
input in this mode. The serial bitstream must be setup at the
DIN input pin a short time before each rising edge of the
externally generated CCLK.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
Virtex-II Pro™ Platform FPGAs: Functional Description
Slave-Serial Mode
Master-Serial Mode
Slave SelectMAP Mode
Master SelectMAP Mode
Boundary-Scan (JTAG, IEEE 1532) Mode
Table 26, page
50.
DS031_60_110200
49