XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 21

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

shadow arrays allow single-cycle address translation and
also help to avoid TLB contention between load/store and
instruction fetch operations. Hardware manages the
replacement and invalidation of shadow-TLB entries; no
system software action is required.
Memory Protection
When address translation is enabled, the translation mech-
anism provides a basic level of protection.
The Zone Protection Register (ZPR) enables the system
software to override the TLB access controls. For example,
the ZPR provides a way to deny read access to application
programs. The ZPR can be used to classify storage by type;
access by type can be changed without manipulating indi-
vidual TLB entries.
The PowerPC Architecture provides WIU0GE (write-back /
write-through,
endian) storage attributes that control memory accesses,
using bits in the TLB or, when address translation is dis-
abled, storage attribute control registers.
When address translation is enabled, storage attribute con-
trol bits in the TLB control the storage attributes associated
with the current page. When address translation is disabled,
bits in each storage attribute control register control the
storage attributes associated with storage regions. Each
storage attribute control register contains 32 fields. Each
field sets the associated storage attribute for a 128 MB
memory region.
Timers
The PPC405 core contains a 64-bit time base and three tim-
ers, as shown in
•
•
•
The time base counter increments either by an internal sig-
nal equal to the CPU clock rate or by a separate external
timer clock signal. No interrupts are generated when the
time base rolls over. The three timers are synchronous with
the time base.
The PIT is a 32-bit register that decrements at the same rate
as the time base is incremented. The user loads the PIT
register with a value to create the desired delay. When the
register reaches zero, the timer stops decrementing and
generates a PIT interrupt. Optionally, the PIT can be pro-
grammed to auto-reload the last value written to the PIT
register, after which the PIT continues to decrement.
The FIT generates periodic interrupts based on one of four
selectable bits in the time base. When the selected bit
changes from 0 to 1, the PPC405 core generates a FIT
interrupt.
The WDT provides a periodic critical-class interrupt based
on a selected bit in the time base. This interrupt can be used
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Programmable Interval Timer (PIT)
Fixed Interval Timer (FIT)
Watchdog Timer (WDT)
R
cacheability,
Figure
8:
user-defined
0,
guarded,
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1-800-255-7778
for system error recovery in the event of software or system
lockups. Users may select one of four time periods for the
interval and the type of reset generated if the WDT expires
twice without an intervening clear from software. If enabled,
the watchdog timer generates a reset unless an exception
handler updates the WDT status bit before the timer has
completed two of the selected timer intervals.
Figure 8: Relationship of Timer Facilities to Base Clock
Interrupts
The PPC405 provides an interface to an interrupt controller
that is logically outside the PPC405 core. This controller
combines the asynchronous interrupt inputs and presents
them to the core as a single interrupt signal. The sources of
asynchronous
JTAG/debug unit, and any implemented peripherals.
Debug Logic
All architected resources on the PPC405 core can be
accessed through the debug logic. Upon a debug event, the
PPC405 core provides debug information to an external
debug tool. Three different types of tools are supported
depending on the debug mode: ROM monitors, JTAG
debuggers, and instruction trace tools.
In internal (intrusive) debug mode, a debug event enables
exception-handling software at a dedicated interrupt vector
to take over the CPU core and communicate with a debug
tool. The debug tool has read-write access to all registers
and can set hardware or software breakpoints. ROM moni-
tors typically use the internal debug mode.
Virtex-II Pro™ Platform FPGAs: Functional Description
External
Clock
Source
interrupts
0
0
PIT (Decrementer)
TBL (32 bits)
(32 bits)
Bit 11 (2
Bit 15 (2
Bit 19 (2
Bit 23 (2 clocks)
Time Base (Incrementer)
Zero Detect
Bit 3
Bit 7
Bit 11 (2
Bit 15 (2
are
31
31
21
17
13
9
clocks)
clocks)
clocks)
(2
(2
29
25
21
17
external
clocks)
clocks)
clocks)
clocks)
0
TBU (32 bits)
PIT Events
FIT Events
DS083-2_06_062001
signals,
WDT Events
31
the
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