XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 25

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Program
Delay
Figure 13: LVCMOS SelectI/O Standard
R
OBUF
registers
Shared
Program
Current
by all
(O/T) CLK1
(O/T) CLK2
V CCO
(O/T) CE
IBUF
(O/T) 1
(O/T) 2
V CCO
REV
SR
Clamp
Diode
Figure 12: Register / Latch Configuration in an IOB Block
V CCO
40K –
40K –
120K
120K
Keeper
Weak
V CCAUX = 2.5V
V CCINT = 1.5V
DS083-2_07_101801
D1
CE
CK1
D2
CE
CK2
SR REV
SR REV
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FF
LATCH
FF
LATCH
1-800-255-7778
PAD
Q1
Q2
Attribute INIT1
Attribute INIT1
Input/Output Individual Options
Each device pad has optional pull-up/pull-down resistors
and weak-keeper circuit in the LVCMOS SelectI/O configu-
ration, as illustrated in
pull-up and pull-down resistors fall within a range of 40 K
to 120 K
The clamp diode is always present, even when power is not.
The optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low. If the pin is con-
nected to a multiple-source signal, the weak-keeper holds
the signal in its last state if all drivers are disabled. Maintain-
ing a valid logic level in this way eliminates bus chatter. An
enabled pull-up or pull-down overrides the weak-keeper cir-
cuit.
Virtex-II Pro™ Platform FPGAs: Functional Description
DDR MUX
FF1
FF2
INIT0
SRHIGH
SRLOW
INIT0
SRHIGH
SRLOW
when V
CCO
= 2.5V (from 2.38V to 2.63V only).
Figure
Reset Type
SYNC
ASYNC
13. Values of the optional
DS031_25_110300
(OQ or TQ)
25