XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 48

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
CLK90, and CLK270 outputs are not available in high-fre-
quency mode.
High or low-frequency mode is selected by an attribute.
Routing
DCM and MGT Locations/Organization
Virtex-II Pro DCMs and serial transceivers (MGTs) are
placed on the top and bottom of each block RAM and multi-
plier column in some combination, as shown in
The number of DCMs and Rocket I/O transceiver cores total
to twice the number of columns in the device. Refer to
Figure 40, page 42
device.
Table 25: DCM Organization
Place-and-route software takes advantage of this regular
array to deliver optimum system performance and fast com-
pile times. The segmented routing resources are essential
to guarantee IP cores portability and to efficiently handle an
incremental design flow that is based on modular imple-
mentations. Total design time is reduced due to fewer and
shorter design iterations.
Hierarchical Routing Resources
Most Virtex-II Pro signals are routed using the global rout-
ing resources, which are located in horizontal and vertical
routing channels between each switch matrix.
As shown in
ered programmable interconnections, with a number of
resources counted between any two adjacent switch matrix
rows or columns. Fanout has minimal impact on the perfor-
mance of each net.
48
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP50
Device
Figure 52, page
Columns
for an illustration of this in the XC2VP4
12
4
4
6
8
49, Virtex-II Pro has fully buff-
DCMs
4
4
4
8
8
MGTs
Table
16
4
4
8
8
www.xilinx.com
1-800-255-7778
25.
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Dedicated Routing
In addition to the global and local routing resources, dedi-
cated signals are available.
•
•
•
•
•
The long lines are bidirectional wires that distribute
signals across the device. Vertical and horizontal long
lines span the full height and width of the device.
The hex lines route signals to every third or sixth block
away in all four directions. Organized in a staggered
pattern, hex lines can only be driven from one end.
Hex-line signals can be accessed either at the
endpoints or at the midpoint (three blocks from the
source).
The double lines route signals to every first or second
block away in all four directions. Organized in a
staggered pattern, double lines can be driven only at
their endpoints. Double-line signals can be accessed
either at the endpoints or at the midpoint (one block
from the source).
The direct connect lines route signals to neighboring
blocks: vertically, horizontally, and diagonally.
The fast connect lines are the internal CLB local
interconnections from LUT outputs to LUT inputs.
There are eight global clock nets per quadrant. (See
Global Clock Multiplexer Buffers, page
Horizontal routing resources are provided for on-chip
3-state buses. Four partitionable bus lines are provided
per CLB row, permitting multiple buses within a row.
(See
Two dedicated carry-chain resources per slice column
(two per CLB column) propagate carry-chain MUXCY
output signals vertically to the adjacent slice. (See
CLB/Slice Configurations, page
One dedicated SOP chain per slice row (two per CLB
row) propagate ORCY output logic signals horizontally
to the adjacent slice. (See
One dedicated shift-chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See
3-State Buffers, page
Shift Registers, page
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Sum of Products, page
38.)
33.)
38.)
43.)
37.)
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