XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 78

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Switching Characteristics
Table 31: Standard Capacitive Loads
78
Notes:
1.
2.
3.
LVTTL Fast Slew Rate, 2mA drive
LVTTL Fast Slew Rate, 4mA drive
LVTTL Fast Slew Rate, 6mA drive
LVTTL Fast Slew Rate, 8mA drive
LVTTL Fast Slew Rate, 12mA drive
LVTTL Fast Slew Rate, 16mA drive
LVTTL Fast Slew Rate, 24mA drive
LVTTL Slow Slew Rate, 2mA drive
LVTTL Slow Slew Rate, 4mA drive
LVTTL Slow Slew Rate, 6mA drive
LVTTL Slow Slew Rate, 8mA drive
LVTTL Slow Slew Rate, 12mA drive
LVTTL Slow Slew Rate, 16mA drive
LVTTL Slow Slew Rate, 24mA drive
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI 33MHZ 3.3V
PCI 66 MHz 3.3V
GTL
GTLP
HSTL Class I (1.5V and 1.8V)
HSTL Class II (1.5Vand 1.8V
HSTL Class III (1.5Vand 1.8V
HSTL Class IV1.5Vand 1.8V
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
I/O parameter measurements are made with the capacitance values shown above.
I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
Use of IBIS models results in a more accurate prediction of the propagation delay:
a.
b.
c.
d.
e.
Model the output in an IBIS simulation into the standard capacitive load.
Record the relative time to the V
Remove the capacitance, and model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS
models for driven devices.
Record the results from the new simulation.
Compare with the capacitance simulation. The increase or decrease in delay from the capacitive load delay simulation should
be added or subtracted from the value above to predict the actual delay.
OH
or V
Standard
OL
transition of interest.
www.xilinx.com
1-800-255-7778
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
Csl (pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
20
20
20
20
30
30
30
30
0
0
R