TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 30

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TS68EN360MAB

Manufacturer Part Number
TS68EN360MAB
Description
32-bit Communication Controller, 25 or 33 MHz
Manufacturer
Atmel Corporation
Datasheet
30
TS68EN360
Figure 7-11. SRAM: Write Cycle (TRLX = 1, CSNTQ = 1, TCYC = 0)
Note:
Figure 7-12. ASYNC Bus Arbitration – IDLE Bus Case
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
A31-A0
D31-D0
(INPUT)
(INPUT)
BGACK
CLKO1
BCLRO
All timing is shown with respect to 0.8V and 2.0V levels.
BG
AS
BR
PRTY0-PRTY3
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
A31-A0
DSACK0
DSACK1
D31-D0
CLKO1
47A
WEx
R/W
(I/O)
CSx
(I/O)
AS
DS
35
S0
33
20
23
S1
11A
55
9C
22
S2
26
9B
37
47A
47A
S3
31A
14C
47A
46
34
60
12A
S4
S5
25A
13A
17A
47A
61
2113B–HIREL–06/05

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