TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 56

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TS68EN360MAB

Manufacturer Part Number
TS68EN360MAB
Description
32-bit Communication Controller, 25 or 33 MHz
Manufacturer
Atmel Corporation
Datasheet
7.17
Table 7-16.
Notes:
56
Number
70
71A
78A
80A
83A
71
85
86
87
72
73
74
75
76
77
78
79
80
81
82
83
84
88
(1)(3)
(1)
(3)
(3)
(3)
(2)
(4)
(4)
(2)
SI Electrical Specifications
1. The ratio SyncCLK/L1RC LK must be greater than 2.5/1.
2. Where P = 1/CLKO1. Thus for a 25 MHz CLKO1 rate, P = 40 ns.
3. These specs are valid for IDL mode only.
4. The strobes and Txd on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
TS68EN360
Characteristic
L1RCLK, L1TCLK Frequency (DCS = 0)
L1RCLK, L1TCLK Width Low (DCS = 0)
L1RCLK, L1TCLK Width High (DCS = 0)
L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time
L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time)
L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time)
L1RSYNC, L1TSYNC Rise/Fall Time
L1RXD Valid to L1CLK Edge (L1RXD Setup Time)
L1CLK Edge to L1RXD Invalid (L1RXD Hold Time)
L1CLK Edge to L1ST(1-4) Valid
L1SYNC Valid to L1ST(1-4) Valid
L1CLK Edge to L1ST(1-4) Invalid
L1CLK Edge to L1TXD Valid
L1TSYNC Valid to L1TXD Valid
L1CLK Edge to L1TXD High Impedance
L1RCLK, L1TCLK Frequency (DSC = 1)
L1RCLK, L1TCLK Width Low (DSC = 1)
L1RCLK, L1TCLK Width High (DSC = 1)
L1CLK Edge to L1CLKO Valid (DSC = 1)
L1RQ Valid Before Falling Edge of L1TSYNC
L1GR Setup Time
L1RG Hold Time
L1CLK Edge to L1SYNC Valid (FSD = 00, CNT = 0000, BYT = 0,
DSC = 0)
GND = 0 V
(See
Figure 7-46
DC,
T
C
= -55 to +125°C.The electrical specifications in this document are preliminary
to
Figure
7-50)
P+10
P+10
P+10
P+10
Min
42
35
10
42
20
35
10
10
10
10
42
0
1
25.0 MHz
Max
12.5
10
15
15
45
45
45
65
65
42
30
0
P+10
P+10
P+10
P+10
Min
20
35
42
35
10
10
10
10
10
42
42
0
1
33.34 MHz
Max
10
15
15
45
45
45
65
65
42
16
30
0
2113B–HIREL–06/05
L1TCLK
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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