TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 74

• Manufacturer Part Number: TS68EN360MAB
• Description: 32-bit Communication Controller, 25 or 33 MHz
• Manufacturer: Atmel Corporation

8.4
Figure 8-1.
74
Ethernet on QUICC
TS68EN360
CTS = CLSN
CD = RENA
Ethernet Block Diagram
RRJCT
RSTRT
PERIPHERAL BUS
RXD
IMB
The CP provides the communication features of the QUICC. Included are a RISC processor,
four SCCs, two SMCs, one SPI, 2.5K bytes of dual-port RAM, an interrupt controller, a time slot
assigner, three parallel ports, a parallel interface port, four independent baud rate generators,
and fourteen serial DMA channels to support the SCCs, SMCs, and SPI.
The IDMAs provide two channels of general-purpose DMA capability. They offer high-speed
transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge
logic. The RISC controller may access the IDMA registers directly in the buffer chaining modes.
The QUICC IDMAs are similar to, yet enhancements of, the one IDMA channel found on the
TS68302.
The four general-purpose timers on the QUICC are functionally similar to the two general-pur-
pose timers found on the TS68302. However, they offer some minor enhancements, such as the
internal cascading of two timers to form a 32-bit timer. The QUICC also contains a periodic inter-
val timer in the SIM60, bringing the total to five on-chip timers.
The Ethernet protocol is available only on the Ethernet version of the QUICC called the
TS68EN360. The non-Ethernet version of the QUICC is the MC68360. The term “QUICC” is the
overall device name that denotes all versions of the device.
The TS68EN360 is a superset of the MC68360, having the additional option allowing Ethernet
operation on any of the four SCCs. Due to performance reason not ass SCCs can be configured
as Ethernet controller at the same time. The TS68EN360 is not restricted only to Ethernet oper-
ation. HDLC, UART, and other protocols may be used to allow dynamic switching between
protocols. See Appendix A Serial Performance for available SCC performance.
When the MODE bits of the SCC GSMR select the Ethernet protocol, then that SCC performs
the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface func-
tions (see
RECEIVER
CONTROL
UNIT
Figure
RECEIVE
8-1)
SHIFTER
DATA
FIFO
REGISTERS
CONTROL
TRANSMIT
SHIFTER
DATA
FIFO
TRANSMITTER
CONTROL
UNIT
TXD
INTERNAL CLOCKS
AND DEFER
GENERATOR
SLOT TIME
COUNTER
CLOCK
RTS = TENA
CD = RENA
CTS = CLSN
RX CLOCK
TX CLOCK
2113B–HIREL–06/05