TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 64

• Manufacturer Part Number: TS68EN360MAB
• Description: 32-bit Communication Controller, 25 or 33 MHz
• Manufacturer: Atmel Corporation

7.20
Table 7-19.
Notes:
64
Number
123
130
138
139
120
121
122
124
125
126
127
128
129
131
132
133
134
135
136
137
(1)
(1)
(2)
(2)
Ethernet Electrical Specifications
1. SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1
2. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
TS68EN360
Characteristic
CLSN Width High
RCLK1 Rise/Fall Time
RCLK1 Width Low
RCLK1 Width High
RXD1 Setup Time
RXD1 Hold Time
RENA Active Delay (from RCLK1 rising edge of the last
data bit)
RENA Width Low
TCLK1 Rise/Fall Time
TCLK1 Width Low
TCLK1 Width High
TXD1 Active Delay (from TCLK1 rising edge)
TXD1 Inactive Delay (from TCLK1 rising edge)
TENA Active Delay (from TCLK1 rising edge)
TENA Inactive Delay (from TCLK1 rising edge)
RSTRT Active Delay (from TCLK1 falling edge)
RSTRT Inactive Delay (from TCLK1 falling edge)
RRJCT Width Low
CLKO1 Low to SDACK Asserted
CLKO1 Low to SDACK Negated
GND = 0 V
(See
Figure 7-54
DC
Figure 7-54. Ethernet Collision Timing
, T
C
to
= -55 to +125°C. The electrical specifications in this document are preliminary
Figure
7-59)
CLSN (CTS1)
(INPUT)
CLKO1 +
CLKO1 +
CLKO1
CLKO1
5 ns
5 ns
Min
100
40
20
10
10
10
10
10
10
10
–
5
–
1
–
–
25.0 MHz
120
Max
50
50
50
15
15
50
50
50
20
20
–
–
–
–
–
–
–
–
–
–
CLKO1 +
CLKO1 +
CLKO1
CLKO1
5 ns
5 ns
Min
100
40
20
10
10
10
10
10
10
10
–
5
–
1
–
–
33.34 MHz
Max
15
15
50
50
50
50
50
50
20
20
–
–
–
–
–
–
–
–
–
–
2113B–HIREL–06/05
CLKO1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns