TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 6

• Manufacturer Part Number: TS68EN360MAB
• Description: 32-bit Communication Controller, 25 or 33 MHz
• Manufacturer: Atmel Corporation

3.2
Table 1. System Bus Signal Index (Normal Operation)
6
Address
Data
Parity
Memory
Controller
Bus Arbitration
Group
Signal Index
TS68EN360
Signal Name
Address Bus
Address Bus/Byte Write
Enables
Function Codes
Data Bus 31 - 16
Data Bus 15 - 0
Parity 2 - 0
Parity 3/16BM
Parity Error
Chip Select
Row Address Select 7
Interrupt Acknowledge 7
Chip Select 6-0
Row Address Select 6-0
Column Address Select
3 - 0/Interrupt
Acknowledge 1, 2, 3, 6
Bus Request
Bus Grant
Bus Grand Acknowledge
Read-Modify-Write Cycle
Initial Configuration 0
Bus Clear Out/Initial
Configuration 1/Row
Address Select 2
Double-Drive
BCLRO/CONFIG1/
PRTY2-PRTY0
PRTY3/16BM
CAS3-CAS0/
RAS6-RAS0
IACK6,3,2,1
Mnemonic
WE3-WE0
CONFIG0
CS6-CS0
FC3-FC0
D31-D16
RAS2DD
A31-A28
D15-D0
BGACK
A27-A0
PERR
IACK7
RAS7
RMC
BG
CS
BR
Function
Lower 27 bits of address bus. (I/O)
Upper four bits of address bus (I/O), or byte write enable
signals (O)
Identifies the processor state and the address space of the
current bus cycle. (I/O)
Upper 16-bit data bus used to transfer byte or word data.
Used in 16-bit bus mode. (I/O)
Lower 16-bit data bus used to transfer 3-byte or long-word
data. (I/O)
Not used in 16-bit bus mode.
Parity signals for byte writes/reads from/to external memory
module. (I/O)
Parity signals for byte writes/reads from/to external memory
module or defines 16-bit bus mode. (I/O)
Indicates a parity error during a read cycle. (O)
Enables peripherals or DRAMs at programmed addresses (O)
or interrupt level 7 acknowledge line. (O)
Enables peripherals or DRAMs at programmed addresses.
(O)
DRAM column address select or interrupt level acknowledge
lines. (O)
Indicates that an external device requires bus mastership.
(I)
Indicates that the current bus cycle is complete and the
QUICC has relinquished the bus. (O)
Indicates that an external device has assumed bus
mastership. (I)
Identifies the bus cycle as part of an indivisible
read-modify-write operation (I/O) or initial QUICC
configuration select. (I)
Indicates that an internal device requires the external bus
(Open-Drain O) or initial QUICC configuration select (I) or row
address select 2 double-drive output. (O)
(1)
(1)
for accesses to external memory or peripherals.
(1)
2113B–HIREL–06/05