TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 8
TS68EN360MAB
Manufacturer Part Number
TS68EN360MAB
Description
32-bit Communication Controller, 25 or 33 MHz
Manufacturer
Atmel Corporation
Datasheet
1.TS68EN360MAB.pdf
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Table 1. System Bus Signal Index (Normal Operation) (Continued)
Note:
8
Clock and Test
(Cont’d)
Power
--
Group
1. I denotes input, O denotes output and I/O is input/output.
TS68EN360
Signal Name
Three-State
Test Clock
Test Mode Select
Test Data In
Test Data Out
Test Reset
Clock Synthesizer Power
Clock Synthesizer
Ground
Clock Out Power
Clock Out Ground
Special Ground 1
Special Ground 2
System Power Supply
and Return
No Connect
Mnemonic
VCC, GND
GNDSYN
NC4-NC1
VCCSYN
GNDCLK
VCCCLK
GNDS1
GNDS2
TRST
TRIS
TMS
TDO
TCK
TDI
Function
Used to three-state all pins if QUICC is configured as a
master. Always Sampled except during system reset. (I)
Provides a clock for Scan test logic. (I)
Controls test mode operations. (I)
Serial test instructions and test data signal. (I)
Serial test instructions and test data signal. (O)
Provides an asynchronous reset to the test controller. (I)
Power supply to the PLL of the clock synthesizer
Ground supply to the PLL of the clock synthesizer
Power supply to clock out pins
Ground supply to clock out pins
Special ground for fast AC timing on certain system bus
signals
Special ground for fast AC timing on certain system bus
signals
Power supply and return to the QUICC
Four no-connect pins
2113B–HIREL–06/05
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