TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 7

• Manufacturer Part Number: TS68EN360MAB
• Description: 32-bit Communication Controller, 25 or 33 MHz
• Manufacturer: Atmel Corporation

Table 1. System Bus Signal Index (Normal Operation) (Continued)
2113B–HIREL–06/05
Bus Control
Interrupt
Control
System
Control
Clock and Test
Group
Signal Name
Data and Size
Acknowledge
Address Strobe
Data Strobe
Size
Read/Write
Output Enable Address
Multiplex
Interrupt Request
Level 7-1
Autovector/Interrupt
Acknowledge 5
Soft Reset
Hard Reset
Halt
Bus Error
System Clock Out 1
System Clock Out 2
Crystal Oscillator
External Filter Capacitor
Clock Mode Select 1-0
Instruction Fetch/
Development Serial Input
Instruction Pipe 0/
Development Serial
Output
Instruction Pipe 1/Row
Address Select 1
Double-Drive
Breakpoint/Development
Serial Clock
Freeze/Initial
Configuration 2
MODCK1-MODCK0
DSACK1 - DSACK0
FREEZE/CONFIG2
IPIPE1/RAS1DD
BKPT/DSCLK
EXTAL, XTAL
AVEC/IACK5
IFETCH/DSI
IPIPE0/DSO
Mnemonic
IRQ7-IRQ1
SIZ1-SIZ0
OE/AMUX
RESETH
RESETS
CLKO2
CLKO1
BERR
HALT
R/W
XFC
DS
AS
Function
Provides asynchronous data transfer acknowledgement and
dynamic bus sizing (open-drain I/O but driven high before
three-stated)
Indicates that a valid address is on the address bus. (I/O)
During a read cycle, DS indicates that an external device
should place valid data on the data bus. During a write cycle,
DS indicates that valid data is on the data bus. (I/O)
Indicates the number of bytes remaining to be transferred for
this cycle. (I/O)
Indicates the direction of data transfer on the bus. (I/O)
Active during a read cycle indicates that an external device
should place valid data on the data bus (O) or provides a
strobe for external address multiplexing in DRAM accesses if
internal multiplexing is not used. (O)
Provides external interrupt requests to the CPU32+ at priority
levels 7-1. (I)
Autovector request during an interrupt acknowledge cycle
(open-drain I/O) or interrupt level 5 acknowledge line. (O)
Soft system reset. (open-drain I/O)
Hard system reset. (open-drain I/O)
Suspends external bus activity. (open-drain I/O)
Indicates an erroneous bus operation is being attempted.
(open-drain I/O)
Internal system clock output 1. (O)
Internal system clock output 2 - normally 2x CLKO1. (O)
Connections for an external crystal to the internal oscillator
circuit. EXTAL (I), XTAL (O)
Connection pin for an external capacitor to filter the circuit of
the PLL. (I)
Selects the source of the internal system clock. (I) THESE
PINS SHOULD NOT BE SET TO 00
Indicates when the CPU32+ is performing an instruction word
prefetch (O) or input to the CPU32+ background debug mode.
(I)
Used to track movement of words through the instruction
pipeline (O) or output from the CPU32+ background debug
mode. (O)
Used to track movement of words through the instruction
pipeline (O), or a row address select 1 “double-drive” output
(O)
Signals a hardware breakpoint to the QUICC (open-drain I/O),
or clock signal for CPU32+ background debug mode (I)
Indicates that the CPU32+ has acknowledged a breakpoint
(O), or initial QUICC configuration select (I)
TS68EN360
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