TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 71
TS68EN360MAB
Manufacturer Part Number
TS68EN360MAB
Description
32-bit Communication Controller, 25 or 33 MHz
Manufacturer
Atmel Corporation
Datasheet
1.TS68EN360MAB.pdf
(83 pages)
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7.24
Table 7-23.
Figure 7-65. Test Clock Input Timing Diagram
Figure 7-66. TRST Timing Diagram
2113B–HIREL–06/05
Number
10
11
12
13
14
15
1
2
3
6
7
8
9
JTAG Electrical Specifications
Characteristic
TCK Frequency of Operation
TCK Cycle Time in Crystal Mode
TCK Clock Pulse Width Measured at 1.5V
TCK rise and Fall Times
Boundary Scan Input Data Setup Time
Boundary Scan Input Data Hold Time
TCK Low to Output Data Valid
TCK Low to Output High Impedance
TMS, TDI Data Setup Time
TMS, TDI Data Hold Time
TCK Low to TDO Data Valid
TCK Low to TDO High Impedance
TRST Assert Time
TRST Setup Time to TCK Low
(INPUT)
TCK
GND = 0 V
(See
Figure 7-65
(INPUT)
(INPUT)
3
TRST
TCK
DC
V
IL
, T
V
IH
C
= -55 to +125°C. The electrical specifications in this document are preliminary
and
Figure
7-68)
14
3
VM
2
15
1
Min
100
40
18
10
18
10
10
40
0
0
0
0
0
0
25.0 MHz
Max
2
VM
20
25
30
40
20
–
–
3
–
–
–
–
–
–
Min
100
40
10
10
10
40
18
18
0
0
0
0
0
0
33.34 MHz
TS68EN360
Max
25
30
40
20
20
–
–
3
–
–
–
–
–
–
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
71
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