upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 295

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

15.2 Standby Function Operation
15.2.1 HALT mode
(1) HALT mode
Notes 1.
Item
System clock
CPU
Port (output latch)
16-bit timer/event counter 00
8-bit timer/event counter 50
8-bit timer H0
8-bit timer H1
Watchdog
timer
A/D converter
Serial interface
Clock monitor
Power-on-clear function
Low-voltage detection function
External interrupt
The HALT mode is set by executing the HALT instruction. HALT mode can be set when the CPU clock before
the setting was the high-speed system clock or internal oscillation clock.
The operating statuses in the HALT mode are shown below.
2.
3.
When “Stopped by software” is selected for the internal oscillator by the option byte and the internal
oscillator is stopped by software (for the option byte, see CHAPTER 20 OPTION BYTE).
“Internal oscillator cannot be stopped” or “Internal oscillator can be stopped by software” can be selected
by the option byte.
µ
PD78F0102H and 78F0103H only.
Internal oscillator
cannot be stopped
Internal oscillator can
be stopped
HALT Mode Setting
Note 2
UART0
UART6
CSI10
Note 2
Note 3
Table 15-2. Operating Statuses in HALT Mode
Operation stopped
Holds the status before HALT mode was set
Operable
Operable
Operable
Operable
Operable
Operation stopped
Operable
Clock supply to the CPU is stopped
Operable
Operable
Operable
Operable
Operable
Operable
Operable
When HALT Instruction Is Executed While
Oscillation Clock
When Internal
CPU Is Operating Using High-Speed
CHAPTER 15 STANDBY FUNCTION
Continues
User’s Manual U16846EJ3V0UD
System Clock
Operation stopped
Oscillation Clock
When Internal
Stopped
−
Note 1
Operation not guaranteed
Operation not guaranteed when count
clock other than TI50 is selected
Operation not guaranteed when count
clock other than TM50 output is selected
during 8-bit timer/event counter 50
operation
Operation not guaranteed when count
clock other than f
Operable
Operation not guaranteed
Operation not guaranteed when serial
clock other than TM50 output is selected
during 8-bit timer/event counter 50
operation
Operation not guaranteed when serial
clock other than external SCK10 is
selected
Operable
High-Speed System
When HALT Instruction Is Executed While
CPU Is Operating on Internal Oscillation
Clock Oscillation
Continues
R
/2
Clock
7
is selected
Operation stopped
High-Speed System
Clock Oscillation
Stopped
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