upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 423

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16-bit
timer/event
counter 00
(TM00)
8-bit
timer/event
counter 50
(TM50)
Function
Details of Function
Capture operation
Compare
operation
Edge detection
CR50: 8-bit timer
compare register
50
TCL50: Timer
clock selection
register 50
TMC50: 8-bit
timer mode
control register 50
Interval
timer/square wave
output
PWM output
Timer start error
If the TI000 pin valid edge is specified as the count clock, a capture operation by the
capture register specified as the trigger for TI000 is not possible.
To ensure the reliability of the capture operation, the capture trigger requires a pulse two
cycles longer than the count clock selected by prescaler mode register 00 (PRM00).
The capture operation is performed at the falling edge of the count clock. An interrupt
request input (INTTM000/INTTM010), however, is generated at the rise of the next count
clock.
A capture operation may not be performed for CR000/CR010 set in compare mode even if
a capture trigger has been input.
If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or
both the rising and falling edges are specified as the valid edge of the TI000 or TI010 pin to
enable the 16-bit timer counter 00 (TM00) operation, a rising edge is detected immediately
after the operation is enabled. Be careful therefore when pulling up the TI000 or TI010 pin.
However, when re-enabling operation after the operation has been stopped, the rising edge
is not detected if the TI000 or TI010 pin is high level.
The sampling clock used to eliminate noise differs when the TI000 pin valid edge is used as
the count clock and when it is used as a capture trigger. In the former case, the count clock
is f
(PRM00). The capture operation is started only after a valid level is detected twice by
sampling the valid edge, thus eliminating noise with a short pulse width.
In the clear & start mode entered on a match of TM50 and CR50 (TMC506 = 0), do not
write other values to CR50 during operation.
In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock
selected by TCL50) or more.
When the internal oscillation clock is selected as the clock to be supplied to the CPU, the
clock of the internal oscillator is divided and supplied as the count clock. If the count clock
is the internal oscillation clock, the operation of 8-bit timer/event counter 50 is not
guaranteed.
When rewriting TCL50 to other than the same data, stop the timer operation beforehand.
Be sure to set bits 3 to 7 to 0.
The settings of LVS50 and LVR50 are valid in other than PWM mode.
Do not make settings <1> to <4> below simultaneously. In addition, follow the setting
procedure shown below.
<1> Setting of TMC501 and TMC506: Setting of operation mode
<2> Setting of TOE50 if enabling output: Enabling timer output
<3> Setting of LVS50 and LVR50 (see Caution 1): Setting of timer output F/F
<4> Setting of TCE50
Stop operation before rewriting TMC506.
Do not write other values to CR50 during operation.
In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock
selected by TCL50) or more.
When reading from CR50 between <1> and <2> in Figure 7-11, the value read differs from
the actual value (read value: M, actual value of CR50: N).
An error of up to one clock may occur in the time required for a match signal to be
generated after timer start. This is because 8-bit timer counter 50 (TM50) is started
asynchronously to the count clock.
X
, and in the latter case the count clock is selected by prescaler mode register 00
APPENDIX D LIST OF CAUTIONS
User’s Manual U16846EJ3V0UD
Cautions
p. 140
p. 140
p. 140
p. 140
p. 140
p. 140
p. 143
p. 143
p. 144
p. 144
p. 144
p. 146
p. 146
p. 146
pp. 147,
150
p. 151
p. 153
p. 153
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