upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 420

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

420
16-bit
timer/event
counter 00
(TM00)
Function
Details of Function
CR000: 16-bit
timer
capture/compare
register 000
CR010: 16-bit
timer
capture/compare
register 010
TMC00: 16-bit
timer mode
control register 00
CRC00:
Capture/compare
control register 00
TOC00: 16-bit
timer output
control register 00
Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a
match of TM00 and CR000.
If CR000 is set to 0000H in the free-running mode and in the clear mode using the valid
edge of the TI000 pin, an interrupt request (INTTM000) is generated when the value of
CR000 changes from 0000H to 0001H following TM00 overflow (FFFFH). Moreover,
INTTM000 is generated after a match of TM00 and CR000 is detected, a valid edge of the
TI010 pin is detected, and the timer is cleared by a one-shot trigger.
When the TI010 pin valid edge is used, P01 cannot be used as the timer output pin (TO00).
When P01 is used as the TO00 pin, the TI010 pin valid edge cannot be used.
When CR000 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If timer count stop and capture trigger input conflict, the captured data is undefined.
Do not rewrite CR000 during TM00 operation.
If CR010 is cleared to 0000H, an interrupt request (INTTM010) is generated when the value
of CR010 changes from 0000H to 0001H following TM00 overflow (FFFFH). Moreover,
INTTM010 is generated after a match of TM00 and CR010 is detected, a valid edge of the
TI000 pin is detected, and the timer is cleared by a one-shot trigger.
When CR010 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
CR010 can be rewritten during TM00 operation. For details, see Caution 2 in Figure 6-15.
16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are
set to values other than 0, 0 (operation stop mode), respectively. Clear TMC002 and
TMC003 to 0, 0 to stop operation.
Timer operation must be stopped before writing to bits other than the OVF00 flag.
Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00).
If any of the following modes: the mode in which clear & start occurs on match between
TM00 and CR000, the mode in which clear & start occurs at the valid edge of the TI000 pin
or free-running mode is selected, when the set value of CR000 is FFFFH and the TM00
value changes from FFFFH to 0000H, the OVF00 flag is set to 1.
Timer operation must be stopped before setting CRC00.
When the mode in which clear & start occurs on a match between TM00 and CR000 is
selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified
as a capture register.
To ensure that the capture operation is performed properly, the capture trigger requires a
pulse two cycles longer than the count clock selected by prescaler mode register 00
(PRM00).
Timer operation must be stopped before setting other than TOC004.
LVS00 and LVR00 are 0 when they are read.
OSPT00 is automatically cleared after data is set, so 0 is read.
Do not set OSPT00 to 1 other than in one-shot pulse output mode.
A write interval of two cycles or more of the count clock selected by prescaler mode register
00 (PRM00) is required to write to OSPT00 successively.
Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1
simultaneously.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16846EJ3V0UD
Cautions
p. 106
p. 106
p. 106
p. 106
pp. 106,
114, 119,
131
p. 107
p. 107
p. 107
p. 108
p. 109
p. 109
p. 109
p. 110
p. 110
p. 110
p. 111
p. 111
p. 111
p. 111
p. 111
p. 111
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