upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 425

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Watchdog
timer
A/D converter
Function
Details of Function
When “Internal
oscillator cannot
be stopped” is
selected by option
byte
When “Internal
oscillator can be
stopped by
software” is
selected by option
byte
ADM: A/D
converter mode
register
ADS: Analog input
channel
specification
register
ADCR: A/D
conversion result
register
PFM: Power-fail
comparison mode
register
PFT: Power-fail
comparison
threshold register
A/D conversion
Power-fail
detection function
Operating current
in standby mode
Input range of
ANI0 to ANI3
In this mode, operation of the watchdog timer absolutely cannot be stopped even during
STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the internal oscillation
clock can be selected as the count source, so after STOP instruction execution, clear the
watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows. If
this processing is not performed, an internal reset signal is generated when the watchdog
timer overflows after STOP instruction execution.
In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
After HALT/STOP mode is released, counting is started again using the operation clock of
the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time,
the counter is not cleared to 0 but holds its value.
A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the
identical data.
For the sampling time of the A/D converter and the A/D conversion start delay time, see
(11) in 10.6 Cautions for A/D Converter.
If data is written to ADM, a wait cycle is generated. For details, see CHAPTER 27
CAUTIONS FOR WAIT.
Be sure to clear bits 2 to 7 of ADS to 0.
If data is written to ADS, a wait cycle is generated. For details, see CHAPTER 27
CAUTIONS FOR WAIT.
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read the
conversion result following conversion completion before writing to ADM and ADS. Using
timing other than the above may cause an incorrect conversion result to be read.
If data is read from ADCR, a wait cycle is generated. For details, see CHAPTER 27
CAUTIONS FOR WAIT.
If data is written to PFM, a wait cycle is generated. For details, see CHAPTER 27
CAUTIONS FOR WAIT.
If data is written to PFT, a wait cycle is generated. For details, see CHAPTER 27
CAUTIONS FOR WAIT.
Make sure the period of <1> to <3> is 14
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, do not use the first conversion result after <3> in this case.
The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to
FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0.
Make sure the period of <3> to <6> is 14
It is no problem if the order of <3>, <4>, and <5> is changed.
<3> must not be omitted if the power-fail function is used.
The period from <7> to <11> differs from the conversion time set using bits 5 to 3 (FR2 to
FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0.
The A/D converter stops operating in the standby mode. At this time, the operating current
can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode
register (ADM) to 0 (see Figure 10-2).
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AV
and AV
input channel, the converted value of that channel becomes undefined. In addition, the
converted values of the other channels may also be affected.
SS
APPENDIX D LIST OF CAUTIONS
or lower (even in the range of absolute maximum ratings) is input to an analog
User’s Manual U16846EJ3V0UD
Cautions
µ
µ
s or more.
s or more.
REF
or higher
p. 176
p. 177
p. 185
p. 185
p. 185
p. 186
p. 186
p. 186
p. 186
p. 187
p. 187
p. 193
p. 193
p. 193
p. 193
p. 193
p. 193
p. 193
p. 193
p. 196
p. 196
Page
(8/17)
425