upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 433

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Low-voltage
detector (LVI)
Option byte
Flash
memory
Electrical
specifications
(standard
products, (A)
grade
products)
Function
Details of Function
Cautions for low-
voltage detector
IMS: Memory
size switching
register
UART6
FLPMC: Flash
programming
mode control
register
Absolute
Maximum
Ratings
High-speed
system clock
(crystal/ceramic)
oscillator
−
−
In a system where the supply voltage (V
the LVI detection voltage (V
voltage detector is used.
(1) When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the
microcontroller can be arbitrarily set by taking action (a) below.
(2) When used as interrupt
Interrupt requests may be frequently generated. Take action (b) below.
Be sure to set 00H to 0081H, 0082H, 0083H, and 0084H (0081H/1081H, 0082H/1082H,
0083H/1083H, and 0084H/1084H when the boot swap function is used).
If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to
the watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0
(RSTOP) of the internal oscillation mode register (RCM). When 8-bit timer H1 operates
with the internal oscillation clock, the count clock is supplied to 8-bit timer H1 even in the
HALT/STOP mode.
Be sure to clear bits 2 to 7 to 0.
There are differences in noise immunity and noise radiation between the flash memory and
mask ROM versions. When pre-producing an application set with the flash memory
version and then mass-producing it with the mask ROM version, be sure to conduct
sufficient evaluations for the commercial samples (not engineering samples) of the mask
ROM versions.
The initial value of IMS is “setting prohibited (CFH)”. Be sure to set the value shown in
Table 21-2 for each product at initialization. When using the 78K0/KB1+ to evaluate the
program of a mask ROM version of the 78K0/KB1, be sure to set the values shown in
Table 21-2.
When UART6 is selected, the receive clock is calculated based on the reset command sent
from the dedicated flash programmer after the FLMD0 pulse has been received.
Be sure to keep FWEDIS at 0 until writing or erasing of the flash memory is completed.
Make sure that FWEDIS = 1 in the normal mode.
Manipulate FLSPM1 and FLSPM0 after execution branches to the internal RAM. The
address of the flash memory is specified by an address signal from the CPU when
FLSPM1 = 0 or the set value of the firmware written when FLSPM1 = 1. In the on-board
mode, the specifications of FLSPM1 and FLSPM0 are ignored.
Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as V
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Since the CPU is started by the internal oscillation clock after reset is released, check the
oscillation stabilization time of the crystal/ceramic oscillation clock using the oscillation
stabilization time counter status register (OSTC). Determine the oscillation stabilization
time of the OSTC register and oscillation stabilization time select register (OSTS) after
sufficiently evaluating the oscillation stabilization time with the resonator to be used.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16846EJ3V0UD
LVI
), the operation is as follows depending on how the low-
DD
Cautions
) fluctuates for a certain period in the vicinity of
SS
.
p. 327
p. 330
p. 330
p. 330
p. 332
p. 333
p. 346
p. 350
p. 350
p. 350
p. 370
p. 371
p. 371
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