st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 16

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
PRNinitialVal0-1 register, see Table 3.8. If uninitialized by the software, the PRNinitialVal register
defaults to 11 1111 1111 (#3FF) as required for GPS satellites.
The PRNcode0-11 and PRNinitialVal0-1 registers are normally written only when the satellite is
first chosen.
PRNphase0-11 registers
The PRN0-11phase registers determine the relative delay between the receiver master clock, and
the start of the one millisecond repetitive code sequence. The code sequence starts when the
receiver clock counter (invisible to the software except through message timestamps) reaches the
value written to the PRNphase0-11 register. The PRNphase0-11 register must only be written
once per satellite milliseconds-epoch, which varies from the receiver epoch dynamically due to sat-
ellite motion. Synchronism with the software is achieved by reading the register, when a write
enable flag is returned. If not enabled, the write operation is abandoned by the software.
The 19-bit value comprises three fields. The 3 least significant bits represent the fractional-delay in
eighths of a code-chip. The middle 10 bits represent the integer delay in code-chips, 0-1022, with
the value 1023 illegal. The upper 6 most significant bits represent the delay in integer milliseconds.
Note also that the eighth-chip resolution of the code generator is not sufficient for positioning. At
125 ns it represents approximately 40 m of range, over 100 m of position. The software must main-
tain the range measurements around the 1 ns resolution level in a 32-bit field, and send an appro-
priate 19-bit sub-field to the register. Note, care must be taken when calculating this field from a
computed delay, or vice versa, to allow for the missing value 1023. The overall register bit-field can-
not be used mathematically as a single binary number.
PRNphase0-11WrEn registers
The PRNphase0-11WrEn flags are active low flags that record when the PRNphase0-11 register
can be updated. The PRNphaseWrEn flag for a channel is set high when the corresponding PRN-
phase register is written. The flag is reset again when the value written is loaded into the PRN gen-
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PRNphase0-11
Bit
2:0
12:3
18:13
Bit field
FractionalDelay
IntegerDelay
Delay
DSP base address + #40 to #6C
Function
Fractional delay in eighths of a code-chip.
Integer delay in code-chips. Value 0-1022. Note, the value 1023 is illegal.
Delay in integer milliseconds.
Table 3.4 PRNphase0-11 register format
Write only