st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 83

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An even
parity bit will be set, if the modulo-2-sum of the eight data bits is 1. An odd parity bit will be cleared
in this case.
In wake-up mode, received frames are only transferred to the receive buffer register if the ninth bit
(the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be activated and no data will
be transferred.
This feature may be used to control communication in multi-processor systems. When the master
processor wants to transmit a block of data to one of several slaves, it first sends out an address
byte which identifies the target slave. An address byte differs from a data byte in that the additional
ninth bit is a 1 for an address byte and a 0 for a data byte, so no slave will be interrupted by a data
byte. An address byte will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each
slave can examine the 8 least significant bits (LSBs) of the received character (the address). The
addressed slave will switch to 9-bit data mode, which enables it to receive the data bytes that will
be coming (with the wake-up bit cleared). The slaves that are not being addressed remain in 8-bit
data + wake-up bit mode, ignoring the following data bytes.
Transmission
Values to be transmitted are written to the transmit fifo, txfifo, by writing to ASCTxBuffer. The txfifo
is implemented as a 16 deep array of 9 bit vectors.
If the fifos are enabled (the ASCControl(FifoEnable) is set), the txfifo is considered full (ASCSta-
tus(TxFull) is set) when it contains 16 characters. Further writes to ASCTxBuffer in this situation
will fail to overwrite the most recent entry in the txfifo. If the fifos are disabled, the txfifo is consid-
ered full (ASCStatus(TxFull) is set) when it contains 1 character, and a write to ASCTxBuffer in
this situation will overwrite the contents.
If the fifos are enabled, ASCStatus(TxHalfEmpty) is set when the txfifo contains 8 or fewer char-
acters. If the fifos are disabled, it’s set when the txfifo is empty.
Writing anything to ASCTxReset empties the txfifo.
Values are shifted out of the bottom of the txfifo into a 9-bit txshift register in order to be transmit-
ted. If the transmitter is idle (the txshift register is empty) and something is written to the ASCTx-
Buffer so that the txfifo becomes non-empty, the txshift register is immediately loaded from the
txfifo and transmission of the data in the txshift register begins at the next baud rate tick.
start
bit
(LSB)
D0
D1
D2
Figure 15.2 9-bit data frames
D3
D4
D5
D6
D7
Data bit (D8)
Parity bit
Wake-up bit
9th
bit
stop
1st
bit
stop
2nd
bit
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