st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 62

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
10.4 EMI configuration registers
The following is a summary of the configuration registers format. Times are programmed in cycles
or phases: a cycle is one clock cycle, a phase is half a clock cycle.
There are 4 data configuration registers for each of the EMI banks. The base addresses for the EMI
registers is
EMIConfigData0Bank0-3
The EMIConfigData0Bank0-3 registers contain configuration data for each of the EMI banks. The
format of each of the EMIConfigData0 registers is shown in Table 10.3.
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EMIConfigData0Bank0-3
Bit
2:0
4:3
6:5
8:7
10:9
12:11
15:13
Bit field
DeviceType
Portsize
BEactive
OEactive
CEactive
BusReleaseTime
DataDriveDelay
#00002000
Table 10.3 EMIConfigData0 register format - 1 per bank
.
EMI base address + #00, #10, #20, #30
CE/OE/BE
ActiveCode
00
01
10
11
Function
Device type. Sets the format of the configuration register. This must
be set to 001 on the ST20-GP6.
001 = SRAM/peripheral
Port size
00 = reserved
01 = reserved
10 = 16 bit
11 = 8 bit
notMemBE active, see Table 10.4 below.
notMemOE active, see Table 10.4 below.
notMemCE active, see Table 10.4 below.
Duration bus release time. 0 to 3 cycles
Drive delay of data bus for writes. 0 to 7 phases
Table 10.4 Strobe configuration
Strobe activity
Inactive
Active during read only
Active during write only
Active during read and write
Read/Write
Units
-
-
-
-
-
Cycles
Phases