st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 78

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
In addition, the diagnostic controller may take any combination of the following actions:
14.3.4 Hardware single instruction step
The function of single stepping one CPU instruction is performed by using a breakpoint range over
the code to be single stepped. The DCU includes a mechanism to prevent the breakpoint trap han-
dler single-stepping itself. By selecting an inverse range, the effect of single stepping one high level
instruction can be achieved.
14.3.5 Jump trace
Jump tracing monitors code jumps, where a jump is any change in execution flow from the stream
of consecutive instructions stored in memory. A jump may be caused by a program instruction, an
interrupt or a trap.
When the jump occurs, a 32-bit DCU register is loaded with the origin of the jump. This value points
to the instruction which would have been executed next if the jump had not occurred. The CPU may
not have completed the instruction prior to the change in flow. The diagnostic controller can be set
to trace the origin of each jump, the destination, or both.
The DCU copies the details of each jump to a rolling trace buffer in memory. The trace buffer may
be located in host memory, but using target memory will have less impact on performance. The
tracing facility has two modes:
14.3.6 Logic state analyzer (LSA) support
Two signals, TriggerIn and TriggerOut, are provided to support diagnostics with an external LSA.
The action by the DCU on receiving a TriggerIn signal is programmable. The selection of internal
events which trigger a TriggerOut signal is also programmable.
14.3.7 Trigger combinations and sequences
Complex trigger conditions can be programmed. For example:
There is no software intrusion imposed by this mechanism.
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wait until the end of the current instruction, then signal a hardware trap;
signal an immediate hardware trap;
continue without intrusion.
signal on TriggerOut to a logic state analyzer;
send a triggered message via the TAP to the host;
unlock access by the target CPU.
Low intrusion. In this mode the DCU uses dead memory cycles to write the trace into the
buffer. This means that the CPU is not delayed, but some trace information may be lost.
Complete trace. In this mode, the CPU is stalled on every jump to ensure the data can be
written to the buffer. This means that no trace information is lost, but the CPU performance
is affected.
the 5th time that breakpoint 3 is encountered;
enable a watchpoint when a breakpoint occurs.