st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 22

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
minate. The counter is initialized to the number of components before the processes are started.
Each component ends with an endp instruction which decrements and tests the counter. For all but
the last component, the counter is non zero and the component is descheduled. For the last com-
ponent, the counter is zero and the main process continues.
4.3
Priority
The following section describes ‘default’ behavior of the CPU and it should be noted that the user
can alter this behavior, for example, by disabling timeslicing and priority interrupts.
The processor can execute processes at one of two priority levels, one level for urgent (high prior-
ity) processes, one for less urgent (low priority) processes. A high priority process will always exe-
cute in preference to a low priority process if both are able to do so.
High priority processes are expected to execute for a short time. If one or more high priority pro-
cesses are active, then the first on the queue is selected and executes until it has to wait for a com-
munication, a timer input, or until it completes processing.
If no process at high priority is active, but one or more processes at low priority are active, then one
is selected. Low priority processes are periodically timesliced to provide an even distribution of pro-
cessor time between tasks which use a lot of computation.
If there are n low priority processes, then the maximum latency from the time at which a low priority
process becomes active to the time when it starts processing is the order of 2 n timeslice periods. It
is then able to execute for between one and two timeslice periods, less any time taken by high pri-
ority processes. This assumes that no process monopolizes the time of the CPU; i.e. it has fre-
quent timeslicing points.
The specific condition for a high priority process to start execution is that the CPU is idle or running
at low priority and the high priority queue is non-empty.
If a high priority process becomes able to run while a low priority process is executing, the low pri-
ority process is temporarily stopped and the high priority process is executed. The state of the low
priority process is saved into ‘shadow’ registers and the high priority process is executed. When no
further high priority processes are able to run, the state of the interrupted low priority process is re-
loaded from the shadow registers and the interrupted low priority process continues executing.
Instructions are provided on the processor core to allow a high priority process to store the shadow
registers to memory and to load them from memory. Instructions are also provided to allow a pro-
cess to exchange an alternative process queue for either priority process queue (see Table 7.21 on
page 49). These instructions allow extensions to be made to the scheduler for custom run-time ker-
nels.
A low priority process may be interrupted after it has completed execution of any instruction. In
addition, to minimize the time taken for an interrupting high priority process to start executing, the
potentially time consuming instructions are interruptible. Also some instructions may be aborted,
and are restarted when the process next becomes active (refer to the Instruction Set chapter).
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