st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 34

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
TriggerMode register
Each interrupt channel can be programmed to trigger on rising/falling edges or high/low levels on
the external Interrupt.
Note, level triggering is different to edge triggering in that if the input is held at the triggering level, a
continuous stream of interrupts is generated.
Mask register
An interrupt mask register is provided in the interrupt controller to selectively enable or disable
external interrupts. This mask register also includes a global interrupt disable bit to disable all
external interrupts whatever the state of the individual interrupt mask bits.
To complement this the interrupt controller also includes an interrupt pending register which con-
tains a pending flag for each interrupt channel. The Mask register performs a masking function on
the Pending register to give control over what is allowed to interrupt the CPU while retaining the
ability to continually monitor external interrupts.
On start-up, the Mask register is initialized to zeros, thus all interrupts are disabled, both globally
and individually. When a 1 is written to the GlobalEnable bit, the individual interrupt bits are still
disabled and must also have a 1 individually written to the InterruptEnable bit to enable the
respective interrupt.
The Mask register is mapped onto two additional addresses so that bits can be set or cleared indi-
vidually.
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TriggerMode
Bit
Mask
Bit
2:0
7:0
16
15:8
Bit field
Bit field
Trigger
Interrupt7:0Enable
GlobalEnable
Table 5.2 TriggerMode register format - one register per interrupt
Function
Control the triggering condition of the Interrupt, as follows:
Function
When set to 1, interrupt is enabled. When 0, interrupt is disabled.
When set to 1, the setting of the interrupt is determined by the specific
InterruptEnable bit. When 0, all interrupts are disabled.
Reserved, write 0.
Interrupt controller base address + #40 to #5C
Trigger2:0
Interrupt controller base address + #C0
Table 5.3 Mask register format
000
001
010
011
100
101
110
111
Interrupt triggers on
No trigger mode
High level - triggered while input high
Low level - triggered while input low
Rising edge - low to high transition
Falling edge - high to low transition
Any edge - triggered on rising and falling edges
No trigger mode
No trigger mode
Read/Write
Read/Write