st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 20

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
Expressions are evaluated on the evaluation stack, and instructions refer to the stack implicitly. For
example, the add instruction adds the top two values in the stack and places the result on the top of
the stack. The use of a stack removes the need for instructions to explicitly specify the location of
their operands. No hardware mechanism is provided to detect that more than three values have
been loaded onto the stack; it is easy for the compiler to ensure that this never happens.
Note that a location in memory can be accessed relative to the workspace pointer, enabling the
workspace to be of any size.
The use of shadow registers provides fast, simple and clean context switching.
4.2
The following section describes ‘default’ behavior of the CPU and it should be noted that the user
can alter this behavior, for example, by disabling timeslicing, installing a user scheduler, etc.
A process starts, performs a number of actions, and then either stops without completing or termi-
nates complete. Typically, a process is a sequence of instructions. The CPU can run several pro-
cesses in parallel (concurrently). Processes may be assigned either high or low priority, and there
may be any number of each.
The processor has a microcoded scheduler which enables any number of concurrent processes to
be executed together, sharing the processor time. This removes the need for a software kernel,
although kernels can still be written if desired.
At any time, a process may be
The scheduler operates in such a way that inactive processes do not consume any processor time.
Each active high priority process executes until it becomes inactive. The scheduler allocates a por-
tion of the processor’s time to each active low priority process in turn (see section 4.3). Active pro-
cesses waiting to be executed are held in two linked lists of process work spaces, one of high
priority processes and one of low priority processes. Each list is implemented using two registers,
one of which points to the first process in the list, the other to the last. In the linked process list
shown in Figure 4.2, process S is executing and P , Q and R are active, awaiting execution. Only the
low priority process queue registers are shown; the high priority process ones behave in a similar
manner.
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Processes and concurrency
active
inactive
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being executed,
interrupted by a higher priority process,
on a list waiting to be executed.
waiting to input,
waiting to output,
waiting until a specified time.