st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 84

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
At the time the transmitter is just about to transmit the stop bits, then if the txfifo is non-empty, the
txshift register will be immediately loaded from the txfifo, and transmission of this new data will
begin as soon as the current stop bit period is over (i.e. the next start bit will be transmitted imme-
diately following the current stop bit period). Thus back-to-back transmission of data can take
place. If instead the txfifo is empty at this point, then the txshift register will become empty. ASC-
Status(TxEmpty) indicates whether the txshift register is empty.
After changing the fifoenable bit, it is important to reset the fifo to empty (by writing to the
ASCTxReset register), since the state of the fifo pointer may be garbage.
The loop-back option (selected by the ASCControl(LoopBack) bit) internally connects the output
of the transmitter shift register to the input of the receiver shift register. This may be used to test
serial communication routines at an early stage without having to provide an external network.
Reception
Reception is initiated by a falling edge on the data input pin (RXD), provided that the ASCCon-
trol(Run) and ASCControl(RxEnable) bits are set. The RXD pin is sampled at 16 times the rate of
the selected baud rate. A majority decision of the first, second and third samples of the start bit
determines the effective bit value. This avoids erroneous results that may be caused by noise.
If the detected value is not a 0 when the start bit is sampled, the receive circuit is reset and waits
for the next falling edge transition at the RXD pin. If the start bit is valid, the receive circuit contin-
ues sampling and shifts the incoming data frame into the receive shift register. For subsequent
data and parity bits, the majority decision of the seventh, eighth and ninth samples in each bit time
is used to determine the effective bit value.
For 0.5 stop bits, the majority decision of the third, fourth, and fifth samples during the stop bit is
used to determine the effective stop bit value.
For 1 and 2 stop bits, the majority decision of the seventh, eighth, and ninth samples during the
stop bits is used to determine the effective stop bit values.
For 1.5 stop bits, the majority decision of the fifteenth, sixteenth, and seventeenth samples during
the stop bits is used to determine the effective stop bit value.
The effective values received on the RXD pin are shifted into a 10-bit rxshift register.
The receive fifo, rxfifo, is implemented as a 16 deep array of 10-bit vectors (each 9 down to 0). If the
rxfifo is empty, ASCstatus(RxBufFull) is set to ‘0’. If the rxfifo is not empty, a read from ASCRx-
Buffer will get the oldest entry in the rxfifo. If fifos are disabled, the rxfifo is considered full when it
contains one character. ASCStatus(RxFifoNearFull) is set when the rxfifo contains more than 8
characters. Writing anything to ASCRxReset empties the rxfifo.
As soon as the effective value of the last stop bit has been determined, the content of the rxshift
register is transferred to the rxfifo (unless we’re in wake-up mode, in which case this happens only
if the wake-up bit, bit8, is a ‘1’). The receive circuit then waits for the next start bit (falling edge tran-
sition) at the RXD pin.
ASCStatus(OverrunError) is set when the rxfifo is full and a character is loaded from the rxshift
register into the rxfifo. It is cleared when the ASCRxBuffer register is read.
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