ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 116

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Coarse Phase Limit Enable (CLEN). This configuration bit enables the coarse phase limit specified in the
COARSELIM[3:0] field. This field controls both T0 and T4. See Section 7.7.6.
Bit 6: Multicycle Phase Detector Enable (MCPDEN). This configuration bit enables the multicycle phase detector
and allows the DPLL to tolerate large-amplitude jitter and wander. The range of this phase detector is the same as
the coarse phase limit specified in the COARSELIM[3:0] field. This field controls both T0 and T4. See Section
7.7.5.
Bit 5: Use Multicycle Phase Detector in the DPLL Algorithm (USEMCPD). This configuration bit enables the
DPLL algorithm to use the multicycle phase detector so that a large phase measurement drives faster DPLL pull-in.
When USEMCPD = 0, phase measurement is limited to ±360°, giving slower pull-in at higher frequencies but with
less overshoot. When USEMCPD = 1, phase measurement is set as specified in the COARSELIM[3:0] field, giving
faster pull-in. MCPDEN should be set to 1 when USEMCPD = 1. This field controls both T0 and T4. See Section
7.7.5.
Bits 3 to 0: Coarse Phase Limit (COARSELIM[3:0]). This field specifies the coarse phase limit and the tracking
range of the multicycle phase detector. The CLEN bit enables this feature. If jitter tolerance greater than 0.5UI is
required and the input clock is a high-frequency signal, the DPLL can be configured to track phase errors over
many UI using the multicycle phase detector. This field controls both T0 and T4. See Section
Rev: 012108
____________________________________________________________________________________________ DS3102
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0000 = ±1UI
0001 = ±3UI
0010 = ±7UI
0011 = ±15UI
0100 = ±31UI
0101 = ±63UI
0110 = ±127UI
0111 = ±255UI
1000 = ±511UI
1001 = ±1023UI
1010 = ±2047UI
1011 = ±4095UI
1100–1111 = ±8191UI
CLEN
7
1
MCPDEN
6
0
PHLIM2
Phase Limit Register 2
74h
USEMCPD
5
0
—
4
0
3
0
COARSELIM[3:0]
2
1
7.7.5
1
0
and 7.7.6.
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0
1