ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 16

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Table 6-5. JTAG Interface Pin Descriptions
See Section
Table 6-6. Power-Supply Pin Descriptions
Note 1: All pin names with an overbar (e.g., RST) are active low.
Note 2: All pins, except power and analog pins, are CMOS/TTL, unless otherwise specified in the pin description.
Note 3: All digital pins, except OCn, are I/O pins in JTAG mode. OCn pins do not have JTAG functionality.
Rev: 012108
____________________________________________________________________________________________ DS3102
PIN NAME
PIN NAME
AVDD_PLL1
AVDD_PLL2
AVDD_PLL3
AVDD_PLL4
AVSS_PLL1
AVSS_PLL2
AVSS_PLL3
AVSS_PLL4
VDD_OC45
VDD_OC67
VSS_OC45
VSS_OC67
JTCLK
JTRST
V
JTDO
JTMS
V
JTDI
V
DDIOB
V
DDIO
DD
SS
9
for functional description and Section
(1)
(1)
PIN TYPES
I = input pin
I
I
I
I/O = input/output pin
IO
IO
O = output pin
O
O
P = power-supply pin
DIFF
PD
PU
3
DIFF
PD
PU
= output pin that can placed in a high-impedance state
= input pin with internal 50kΩ pulldown
= input pin with internal 50kΩ pullup
= input pin that is LVDS/LVPECL differential signal compatible
= input/output pin with internal 50kΩ pulldown
= input/output pin with internal 50kΩ pullup
= output pin that is LVDS/LVPECL differential signal compatible
TYPE
TYPE
I
I
O
I
PU
PU
PU
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
I
3
(2)
(2)
JTAG Test Reset (Active Low). Asynchronously resets the test access port (TAP) controller. If
not used, JTRST can be held low or high.
JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If
not used, JTCLK can be held low or high.
JTAG Test Data Input. Test instructions and data are clocked in on this pin on the rising edge
of JTCLK. If not used, JTDI can be held low or high.
JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling
edge of JTCLK. If not used, leave floating.
JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port
into the various defined IEEE 1149.1 states. If not used connect to V
Core Power Supply. 1.8V ±10%.
I/O Power Supply. 3.3V ±5%.
Power for Pins OC1B to OC5B. Voltage can be from 2.5V ±5% to 3.3V ±5%.
Ground Reference
Power Supply for Differential Outputs OC4POS/NEG and OC5POS/NEG. 1.8V ±10%.
Return for Differential Outputs OC4POS/NEG and OC5POS/NEG
Power Supply for Differential Outputs OC6POS/NEG and OC7POS/NEG. 1.8V ±10%.
Return for LVDS Differential Outputs OC6POS/NEG and OC7POS/NEG
Power Supply for Master Clock Generator APLL. 1.8V ±10%.
Return for Master Clock Generator APLL
Power Supply for T0 APLL. 1.8V ±10%.
Return for T0 APLL
Power Supply for T4 APLL. 1.8V ±10%.
Return for T4 APLL
Power Supply for T0 APLL2. 1.8V ±10%.
Return for T0 APLL2
10.5
for timing specifications.
PIN DESCRIPTION
PIN DESCRIPTION
DDIO
or leave floating.
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