ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 24

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

In nonrevertive mode, planned switchover to a newly valid higher priority input clock can be done manually under
software control. The validation of the new higher priority clock sets the corresponding status bit in the
MSR2
respond to this change of state by briefly enabling revertive mode (toggling REVERT high then back low) to drive
the switchover to the higher priority clock.
In most systems redundant timing cards are required, with one functioning as the master and the other as the
slave. In such systems the priority tables of the master and slave must match. The register set makes it easy for
the slave’s priority table to track the master’s table. At system start-up, the same priorities must be assigned to the
input clocks, for both DPLLs, in the master and slave devices. During operation, if an input clock becomes valid or
invalid in one device (master or slave), the change is flagged in that device’s
drive an interrupt request on the INTREQ pin if needed. The real-time valid/invalid state of the input clocks can then
be read from that device’s
control bits of the other device’s
other device as well.
7.6.3 Forced Selection
The T0FORCE field in the
specified input clock to be the selected reference for the T0 and T4 DPLLs, respectively. In both T0FORCE and
T4FORCE, values of 0 and 15 specify normal operation with automatic reference selection. Values from 1 to 6 and
8 and 9 specify the input clock to be the forced selection; other values will cause no input to be selected. Internally,
forcing is accomplished by giving the specified clock the highest priority (as specified in PTAB1:REF1). In revertive
mode (MCR3:REVERT = 1) the forced clock automatically becomes the selected reference (as specified in
PTAB1:SELREF) as well. In nonrevertive mode (T0 DPLL only) the forced clock only becomes the selected
reference when the existing selected reference is invalidated or made unavailable for selection. In both revertive
and nonrevertive modes when an input is forced to be the highest priority, the normal highest priority input (when
no input is forced) is listed as the second-highest priority (PTAB2:REF2) and the normal second-highest priority
input is listed as the third-highest priority (PTAB2:REF3).
When the T4 DPLL is used to measure the phase difference between the T0 DPLL selected reference and another
reference input by setting the T0CR1:T4MT0 bit, the T4FORCE field in the
other reference input.
7.6.4 Ultra-Fast Reference Switching
By default, disqualification of the selected reference and switchover to another reference occurs when the activity
monitor’s inactivity alarm threshold has been crossed, a process that takes on the order of hundreds of
milliseconds or seconds. For the T0 DPLL, an option for extremely fast disqualification and switchover is also
available. When ultra-fast switching is enabled (MCR10:UFSW = 1), if the fast activity monitor detects
approximately two missing clock cycles, it declares the reference failed by forcing the leaky bucket accumulator to
its upper threshold (see Section 7.5.2) and initiates reference switching. This is in addition to setting the SRFAIL
latched status bit in
ultra-fast switching occurs, the T0 DPLL transitions to the prelocked 2 state, which allows switching to occur faster
by bypassing the loss-of-lock state. The device should be in nonrevertive mode when ultra-fast switching is
enabled. If the device is in revertive mode, ultra-fast switching could cause excessive reference switching when the
highest priority input is intermittent.
7.6.5 External Reference Switching Mode
In this mode the SRCSW input pin controls reference switching between two clock inputs. This mode is enabled by
setting the EXTSW bit to 1 in the
lock to input IC3 (if the priority of IC3 is nonzero in IPR2) or IC5 (if the priority of IC3 is zero) whether or not the
selected input has a valid reference signal. If the SRCSW pin is low, the T0 DPLL is forced to lock to input IC4 (if
the priority of IC4 is nonzero in IPR2) or IC6 (if the priority of IC4 is zero) whether or not the selected input has a
valid reference signal. During reset the default value of the EXTSW bit is latched from the SRCSW pin. If external
reference switching mode is enabled during reset, the default frequency tolerance
to ±80ppm rather than the normal default of ±9.2ppm.
Rev: 012108
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register, which can drive an interrupt request on the INTREQ pin if needed. System software can then
MSR2
VALSR1
MCR2
and optionally generating an interrupt request, as described in Section 7.5.3. When
VALCR1
MCR10
register and the T4FORCE field in the
and
VALSR2
register. In this mode, if the SRCSW pin is high, the T0 DPLL is forced to
and
VALCR2
registers. Once the nature of the state change is understood, the
registers can be manipulated to mark clocks invalid in the
MCR4
MCR4
MSR1
register provide a way to force a
register can be used to select the
(DLIMIT
or
MSR2
registers) is configured
register, which can
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MSR1
or