ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 92

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 4: Soft Frequency Alarm Limit (SOFT[3:0]). This field is an unsigned integer that specifies the soft
frequency alarm limit for all input clocks except the T0 DPLL’s selected reference. The soft limit for the selected
reference is specified by SRLIMIT:SOFT[3:0]. The soft alarm limit is only used for monitoring; soft alarms do not
invalidate input clocks. The limit in ppm is ±(SOFT[3:0] + 1) × 3.81. The default limit is ±11.43ppm. Soft alarms are
reported in the SOFT status bits of the
Bits 3 to 0: Hard Frequency Alarm Limit (HARD[3:0]). This field is an unsigned integer that specifies the hard
frequency alarm limit for all input clocks except the T0 DPLL’s selected reference. The hard limit for the selected
reference is specified by SRLIMIT:HARD[3:0]. Hard alarms invalidate input clocks. The limit in ppm
is ±(HARD[3:0] + 1) × 3.81. The default limit is ±15.24ppm. Hard alarms are reported in the HARD status bits of the
ISR
Register Name:
Register Description:
Register Address:
Bit#
Name
Default
Bits 7 to 4: Soft Frequency Alarm Limit (SOFT[3:0]). This field is an unsigned integer that specifies the soft
frequency alarm limit for the T0 DPLL’s selected reference. The soft limit for all other input clocks is specified by
ILIMIT:SOFT[3:0]. The soft alarm limit is only used for monitoring; soft alarms do not invalidate input clocks. The
limit in ppm is ±(SOFT[3:0] + 1) × 3.81. The default limit is ±11.43ppm. Soft alarms are reported in the SOFT status
bits of the
Bits 3 to 0: Hard Frequency Alarm Limit (HARD[3:0]). This field is an unsigned integer that specifies the hard
frequency alarm limit for the T0 DPLL’s selected reference. The hard limit for all other input clocks is specified by
ILIMIT:HARD[3:0]. Hard alarms invalidate input clocks. The limit in ppm is ±(HARD[3:0] + 1) × 3.81. The default
limit is ±15.24ppm. Hard alarms are reported in the HARD status bits of the
Rev: 012108
____________________________________________________________________________________________ DS3102
registers. See Section 7.5.1.
ISR
registers. See Section 7.5.1.
7
0
7
0
6
0
6
0
SOFT[3:0]
SOFT[3:0]
ILIMIT
Input Clock Frequency Limit Register
49h
SRLIMIT
Selected Reference Frequency Limit Register
4Ah
ISR
registers. See Section 7.5.1.
5
1
5
1
4
0
4
0
3
0
0
3
I SR
1
registers. See Section 7.5.1.
2
0
2
0
HARD[3:0]
HARD[3:0]
1
1
1
1
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0
1
0
1