ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 91

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Frequency Monitor Clock Source (FMONCLK). This bit specifies the clock source for the input clock
frequency monitors.
Bit 6: SRFAIL Pin Enable (SRFPIN). When this bit is set to 1, the SRFAIL pin is enabled. When enabled the
SRFAIL pin follows the state of the SRFAIL status bit in the
indication of the failure of the current reference. See Section 7.5.3.
Bit 5: Ultra-Fast Switching Mode (UFSW). See Section 7.6.4.
Bit 4: External Reference Switching Mode (EXTSW). This bit enables external reference switching mode. In this
mode, if the SRCSW pin is high the T0 DPLL is forced to lock to input IC3 (if the priority of IC3 is nonzero) or IC5 (if
the priority of IC3 is zero) whether or not the selected input has a valid reference signal. If the SRCSW pin is low
the device is forced to lock to input IC4 (if the priority of IC4 is nonzero) or IC6 (if the priority of IC4 is zero) whether
or not the selected input has a valid reference signal. During reset the default value of this bit is latched from the
SRCSW pin. This mode only controls the T0 DPLL. The T4 DPLL is not affected. See Section 7.6.5.
Bit 3: Phase Build-Out Freeze (PBOFRZ). This bit freezes the current input-output phase relationship and does
not allow further phase build-out events to occur. This bit affects phase build-out in response to reference switching
(Section 7.7.7.1).
Bit 2: Phase Build-Out Enable (PBOEN). When this bit is set to 1 a phase build-out event occurs every time the
T0 DPLL changes to a new reference, including exiting the holdover and free-run states. When this bit is set to 0,
the T0 DPLL locks to the new source with zero degrees of phase difference. See Section 7.7.7.
Bit 1: Soft Frequency Alarm Enable (SOFTEN). This bit enables input clock frequency monitoring with the soft
alarm limits set in the
registers. See Section 7.5.1.
Bit 0: Hard Frequency Limit Enable (HARDEN). This bit enables input clock frequency monitoring with the hard
alarm limits set in the
registers. See Section 7.5.1.
Rev: 012108
____________________________________________________________________________________________ DS3102
0 = T0 DPLL internal frequency
1 = Internal 204.8MHz master clock
0 = SRFAIL pin disabled (not driven)
1 = SRFAIL pin enabled
0 = Disabled
1 = Enabled. The current reference source is disqualified after less than three missing clock cycles.
0 = Normal operation
1 = External switching mode
0 = Not frozen
1 = Frozen
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
FMONCLK
7
0
ILIMIT
ILIMIT
SRFPIN
and
and
6
0
MCR10
Master Configuration Register 10
48h
SRLIMIT
SRLIMIT
UFSW
registers. Hard alarms are reported in the HARD status bits of the
5
0
registers. Soft alarms are reported in the SOFT status bits of the
see below
EXTSW
4
MSR2
PBOFRZ
3
0
register. This gives the system a very fast
PBOEN
2
1
SOFTEN
1
0
HARDEN
91 of 141
0
1
ISR
ISR