ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 33

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

The T0 DPLL phase detectors can be configured for normal phase/frequency locking (±360° capture) or nearest
edge phase locking (±180° capture). With nearest edge detection the phase detectors are immune to occasional
missing clock cycles. The DPLL automatically switches to nearest edge locking when the multicycle phase detector
is disabled and the other phase detectors determine that phase lock has been achieved. Setting D180 = 1 in the
TEST1
DPLL always has nearest edge locking enabled.
The early/late phase detector, also known as phase detector 2, is enabled and configured in the PD2 fields of
registers
settings of these registers are appropriate for all operating modes. Adjustments only affect small signal overshoot
and bandwidth.
The multicycle phase detector is enabled by setting MCPDEN = 1 in the
MCPD—from ±1UI up to ±8191UI—is configured in the COARSELIM field of PHLIM2. The MCPD tracks phase
position over many clock cycles, giving high jitter tolerance. Thus, the use of the MCPD is an alternative to the use
of LOCK8K mode for jitter tolerance. When a DPLL is direct locking to 8kHz, 4kHz, or 2kHz, or in LOCK8K mode,
the multicycle phase detector is automatically disabled.
When USEMCPD = 1 in PHLIM2, the MCPD is used in the DPLL loop, giving faster pull-in but more overshoot. In
this mode the loop has similar behavior to LOCK8K mode. In both cases large phase differences contribute to the
dynamics of the loop. When enabled by MCPDEN = 1, the MCPD tracks the phase position whether or not it is
used in the DPLL loop.
When the input clock is divided before being sent to the phase detector, the divider output clock edge gets aligned
to the feedback clock edge before the DPLL starts to lock to a new input clock signal or after the input clock signal
has a temporary signal loss. This helps ensure locking to the nearest input clock edge, which reduces output
transients and decreases lock times.
7.7.6 Loss-of-Lock Detection
Loss-of-lock can be triggered by any of the following in both the T0 and T4 DPLLs:
The fine phase-lock detector is enabled by setting FLEN = 1 in the
configured in the FINELIM field of PHLIM1.
The coarse phase-lock detector is enabled by setting CLEN = 1 in the
configured in the COARSELIM field of PHLIM2. This coarse phase-lock detector is part of the multicycle phase
detector (MCPD) described in Section 7.7.5. The COARSELIM field sets both the MCPD range and the coarse
phase limit, since the two are equivalent. If loss-of-lock should not be declared for multiple-UI input jitter, the fine
phase-lock detector should be disabled and the coarse phase-lock detector should be used instead.
The hard frequency limit detector is enabled by setting FLLOL = 1 in the
DPLL is configured in registers
frequency reaches the hard limit, loss-of-lock is declared. The
specify a soft frequency limit. Exceeding the soft frequency limit does not cause loss-of-lock to be declared. When
the T0 DPLL frequency reaches the soft limit, the T0SOFT status bit is set in the
DPLL frequency reaches the soft limit, the T4SOFT status bit is set in OPSTATE. Both the SOFT and HARD alarm
limits have hysteresis as required by GR-1244.
The inactivity detector is enabled by setting NALOL = 1 in the
DPLL declares loss-of-lock after one or two missing clock cycles on the selected reference. See Section 7.5.3.
Rev: 012108
____________________________________________________________________________________________ DS3102
register disables nearest edge locking and forces the T0 DPLL to use phase/frequency locking. The T4
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T0CR2
The fine phase-lock detector (measures phase between input and feedback clocks)
The coarse phase-lock detector (measures whole cycle slips)
Hard frequency limit detector
Inactivity detector
and
T0CR3
for the T0 DPLL and registers
DLIMIT1
and DLIMIT2. The T4 DPLL hard limit is fixed at ±80ppm. When the DPLL
T4CR2
PHLIM1
DLIMIT3
and
PHLIM2
register. When this detector is enabled the
T4CR3
PHLIM1
DLIMIT3
register also has the SOFTLIM field to
PHLIM2
for the T4 DPLL. The reset default
register. The coarse phase limit is
OPSTATE
register. The fine phase limit is
register. The hard limit for the T0
register. The range of the
register. When the T4
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