ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 38

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

7.8.1 Signal Format Configuration
Output clocks OC4, OC5, OC6, and OC7 are LVDS-compatible, LVPECL level-compatible outputs. The type of
output can be selected or the output can be disabled using the OCnSF configuration bits in the
LVPECL level-compatible mode generates a differential signal that is large enough for most LVPECL receivers.
Some LVPECL receivers have a limited common mode signal range which can be accommodated for by using an
AC-coupled signal. The LVDS electrical specifications are listed in
termination is shown in
and the recommended LVPECL receiver termination is shown in
easily interfaced to LVDS, LVPECL, and CML inputs on neighboring ICs using a few external passive components.
See
The other output clocks are CMOS/TTL signal format.
7.8.2 Frequency Configuration
The frequency of output clocks OC1 to OC7 is a function of the settings used to configure the components of the
T0 and T4 PLL paths. These components are shown in the detailed block diagram of
The DS3102 uses digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock
(204.8MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS
output is a coding of the clock output phase that is used by a special circuit to determine where to put the edges of
the output clock between the clock edges of the master clock. The edges of the output clock, however, are not
ideally located in time resulting in jitter with an amplitude typically less than 1ns pk-pk.
7.8.2.1 T0 and T4 DPLL Details
See
synthesize internal clocks from which the output and feedback clocks are derived. The T4 DPLL only has a single
DFS output clock signal for both the output clocks and the feedback clock, whereas there are two DFS output clock
signals in the T0 DPLL—one for the output clocks and one for the feedback clock.
In the T0 DPLL, the feedback clock-signal output handles phase build-out or any phase offset configured in the
OFFSET
may have a phase offset. The T0 and T4 feedback-DFS blocks are always connected to the T0 forward DFS and
the T4 forward DFS, respectively. The feedback-DFS blocks synthesize the appropriate locking frequencies for use
by the phase-frequency detectors (PFDs). See Section 7.4.2.
7.8.2.2 Output DFS and APLL Details
See
blocks, and three APLL DFS blocks. Four of the DFS blocks can be connected to either the T0 DPLL or the T4
DPLL, and three are always connected to the T0 DPLL. The T0 APLL, the T0 APLL2 and the T4 APLL (and their
output dividers) get their frequency references from three associated APLL DFS blocks. All the output DFS blocks
are connected to the T0 DPLL when MCR4:LKT4T0 = 1.
The 2K8K DFS and FSYNC DFS blocks generate both 2kHz and 8kHz signals which have about 1ns pk-pk jitter.
The FSYNC (8kHz) and MFSYNC(2 kHz) signals come from the FSYNC DFS block, which is always connected to
the T0 DPLL when not in independent mode (FSCR2:INDEP = 1). The 2kHz and 8kHz signals available on output
clocks OC1 to OC7 come from the 2K8K DFS, which can be connected to either the T0 DPLL or the T4 DPLL
depending on FSCR1:2K8KSRC and MCR4:LKT4T0.
The DIG1 DFS can generate an N x DS1 or NxE1 signal with about 1ns pk-pk jitter. The DIG2 DFS can generate
an N x DS1, N x E1, 6.312MHz, 10MHz, or N x 19.44MHz clock with approximately 1ns pk-pk jitter. Each DIG12
DFS can be connected to either the T0 DPLL or the T4 DPLL using MCR7:DIG1SRC or MCR7:DIG2SRC and
MCR4:LKT4T0. The frequency of the DIG1 clock is configured by the DIG1SS bit in
in MCR7. The frequency of the DIG2 clock is configured by the DIG2AF and DIG2SS bits in
Rev: 012108
____________________________________________________________________________________________ DS3102
Maxim App Note HFAN-1.0
Figure
Figure
registers. Thus, the T0 DPLL output clock signals and the feedback clock signal are frequency-locked but
7-1. The output clock frequencies are determined by two 2kHz/8kHz DFS blocks, two DIG12 DFS
7-1. The T0 and T4 forward-DFS blocks use the 204.8MHz master clock and DFS technology to
Figure
10-1. The LVPECL level-compatible electrical specifications are listed in
for details.
Figure
Table
10-3. These differential outputs can be
10-5, and the recommended LVDS
MCR6
Figure
and the DIG1F[1:0] field
7-1.
MCR8
MCR6
register. The
Table
38 of 141
and the
10-6,