ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 12

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

5.4
5.5
5.6
5.7
Rev: 012108
____________________________________________________________________________________________ DS3102
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Output APLL Features
Three separate clock multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates,
Fast/Gigabit Ethernet rates, and 10G Ethernet rates, all locked to a common reference clock
The T0 APLL, always connected to the T0 DPLL, has frequency options suitable for N x 19.44MHz,
N x DS1, N x E1, N x 25MHz, and N x 62.5MHz
The T4 APLL can be connected to either the T0 DPLL or the T4 DPLL and has frequency options suitable
for N x 19.44MHz, N x DS1, N x E1, N x DS2, DS3, E3, N x 10MHz, N x 10.24MHz, N x 13MHz,
N x 25MHz, and N x 62.5MHz
The T0 APLL2, always connected to the T0 DPLL, produces 312.5MHz for 10G Synchronous Ethernet
applications
Output Clock Features
Seven output clocks: three CMOS/TTL (≤ 125MHz), two LVDS/LVPECL (≤ 312.50MHz), and two dual
CMOS/TTL and LVDS/LVPECL
Output clock rates include 2kHz, 8kHz, N x DS1, N x E1, DS2, DS3, E3, 6.48MHz, 19.44MHz, 38.88MHz,
51.84MHz, 77.76MHz, 155.52MHz, 311.04MHz, 2.5MHz, 25MHz, 125MHz, 156.25MHz, 312.50MHz,
10MHz, 10.24MHz, 13MHz, 30.72MHz, and various multiples and submultiples of these rates
Custom clock rates also available: any multiple of 2kHz up to 77.76MHz, any multiple of 8kHz up to 311.04MHz,
and any multiple of 10kHz up to 388.79MHz
Three independent output APLLs support simultaneous generation of 155.52MHz for SONET/SDH,
125MHz for Gigabit Ethernet, and 156.25/312.5MHz for 10G Ethernet (plus various multiples/submultiples
of each)
All outputs have < 1ns peak-to-peak output jitter; outputs from APLLs have < 0.5ns peak-to-peak
Each CMOS/TTL clock output has two leads, the standard output (e.g., OC1) with a 3.3V power supply,
and the “B” output (e.g., OC1B) connected to the V
8kHz frame sync and 2kHz multiframe sync outputs have programmable polarity and pulse width and can
be disciplined by a 2kHz or 8kHz sync input
Redundancy Features
Devices on redundant timing cards can be configured for master/slave operation
Clocks and frame syncs can be cross-wired between devices to ensure that slave always tracks master
Input clock priority tables can easily be kept synchronized between master and slave
General Features
Operates from a single external 12.800MHz local oscillator (XO, TCXO, or OCXO)
On-chip watchdog circuit for the local (REFCLK) oscillator
SPI serial microprocessor interface
Four general-purpose I/O pins
Register set can be write protected
DDIOB
power supply for optional 2.5V output signal levels.
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