mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 16

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

CKCON1: Clock Control Register 1
SFR Address
SFR Page
Bit 7: OSCDR, OSC Driving control Register. Reset value is load from OSCDN (in hardware option). If OSCDN in
0: The driving of crystal oscillator is enough for oscillation up to 25MHz.
1: The driving of crystal oscillator is reduced. It will helpful in EMI reduction. Regarding application not needing
Bit 6~5: Reserved.
Bit 4~0: This is set the crystal frequency value to define the time base of ISP/IAP programming. Fill with a proper
value according to OSCin, as listed below.
[XCKS4~XCKS0] = OSCin – 1, where OSCin=1~25 (MHz).
For examples,
(1) If OSCin=12MHz, then fill [XCKS4~XCKS0] with 11, i.e., 001011B.
(2) If OSCin=6MHz, then fill [XCKS4~XCKS0] with 5, i.e., 000101B.
The default value of XCKS= 5’b01010 for OSCin= 11MHz.
AUXR0: Auxiliary Register 0
SFR Address
SFR Page
Bit 7~6: P60 output configured control bit 1 and 0. The two bits only act when internal RC oscillator is selected for
system clock source. In this condition, XTAL2 and XTAL1 are the alternated function for P60 and P61. P60
provides the following selections for GPIO or clock source generator. When P60OC[1:0] index to non-P60
function, XTAL2 will drive the on-chip RC oscillator output to provide the clock source for other devices.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
16/84
P60OC1
OSCDR
high frequency clock, below 16MHz, it is recommended to do so.
R/W
R/W
7
7
hardware option is enabled, the OSCDR is set to “1” after power on. Otherwise, it is set to “0”. And it could
be read/written by CPU.
MEGAWIN
MAKE YOU WIN
P60OC0
= 0xBF
= All
= 0x8E
= All
P60OC[1:0]
R/W
--
6
R
6
22MHz
23MHz
24MHz
25MHz
OSCin
1MHz
2MHz
3MHz
4MHz
……
00
01
10
11
P60FD
R/W
--
5
R
5
XTAL2 function
INTOSC/2
INTOSC/4
INTOSC
XCKS4
P34FD
P60
R/W
R/W
4
4
Reset Value = xxx0-1010
Reset Value = 0000-0000
XCKS[4:0]
5’b00000
5’b00001
5’b00010
5’b10101
5’b00011
5’b10110
5’b11000
5’b10111
……
XCKS3
R/W
R/W
--
3
3
Quasi-bidirectional I/O
Push-Pull Output
Push-Pull Output
Push-Pull Output
I/O mode
XCKS2
R/W
R/W
--
2
2
XCKS1
MG82FE(L)308/316
R/W
R/W
1
1
--
Preliminary, v 0.04
XCKS0
R/W
R/W
--
0
0